Improving STM32F746G-Discovery board files

2 files changed, 68 insertions, 112 deletions

diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
index 51e59936..ae002598 100644
--- a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
+++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
@@ -1,112 +1,67 @@
-#include "../../../gfx.h"
-#undef Red
-#undef Green
-#undef Blue
-#include "stm32f7xx_hal.h"
-
-#if GFX_USE_OS_CHIBIOS
-	#define HAL_GPIO_Init(port, ptr)	palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
-#else
-	systemticks_t gfxSystemTicks(void)
-	{
-		return HAL_GetTick();
-	}
-
-	systemticks_t gfxMillisecondsToTicks(delaytime_t ms)
-	{
-		return ms;
-	}
-#endif
-
-static void SystemClock_Config(void);
-
-void Raw32OSInit(void) {
-    /* Enable the CPU Cache's */
-	SCB_EnableICache();	// Enable I-Cache
-	SCB_EnableDCache();	// Enable D-Cache
-
-
-    /* STM32F7xx HAL library initialization:
-         - Configure the Flash ART accelerator on ITCM interface
-         - Configure the Systick to generate an interrupt each 1 msec
-         - Set NVIC Group Priority to 4
-         - Global MSP (MCU Support Package) initialization
-       */
-    HAL_Init();
-
-    /* Configure the system clock to 216 MHz */
-    SystemClock_Config();
-
-#if !GFX_USE_OS_CHIBIOS
-    // LED - for testing
-	GPIO_InitTypeDef  GPIO_InitStruct;
-	GPIO_InitStruct.Pin = GPIO_PIN_1;
-	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-	GPIO_InitStruct.Pull = GPIO_NOPULL;
-	GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
-    __GPIOI_CLK_ENABLE();
-	HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
-#endif
-
-}
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 200000000	/ 216000000
-  *            HCLK(Hz)                       = 200000000	/ 216000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 4
-  *            APB2 Prescaler                 = 2
-  *            HSE Frequency(Hz)              = 25000000
-  *            PLL_M                          = 25
-  *            PLL_N                          = 400			/ 432
-  *            PLL_P                          = 2
-  *            PLL_Q                          = 8			/ 9
-  *            VDD(V)                         = 3.3
-  *            Main regulator output voltage  = Scale1 mode
-  *            Flash Latency(WS)              = 6			/ 7
-  * @param  None
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-  __PWR_CLK_ENABLE();
-
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = 12;
-  RCC_OscInitStruct.PLL.PLLN = 192;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 2;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  HAL_PWREx_ActivateOverDrive();
-
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6);
-
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
-  PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
-
-  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
-}
+#include "../../../gfx.h"

+#undef Red

+#undef Green

+#undef Blue

+#include "stm32f7xx_hal.h"

+

+#if GFX_USE_OS_CHIBIOS

+	#define HAL_GPIO_Init(port, ptr)	palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))

+#else

+	systemticks_t gfxSystemTicks(void)

+	{

+		return HAL_GetTick();

+	}

+

+	systemticks_t gfxMillisecondsToTicks(delaytime_t ms)

+	{

+		return ms;

+	}

+#endif

+

+void SystemClock_Config(void)

+{

+  RCC_ClkInitTypeDef RCC_ClkInitStruct;

+  RCC_OscInitTypeDef RCC_OscInitStruct;

+

+  /* Enable HSE Oscillator and activate PLL with HSE as source */

+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;

+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;

+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

+  RCC_OscInitStruct.PLL.PLLM = 25;

+  RCC_OscInitStruct.PLL.PLLN = 432;

+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;

+  RCC_OscInitStruct.PLL.PLLQ = 9;

+  HAL_RCC_OscConfig(&RCC_OscInitStruct);

+

+  /* Activate the OverDrive to reach the 216 MHz Frequency */

+  HAL_PWREx_EnableOverDrive();

+

+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */

+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);

+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;

+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;

+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);

+}

+

+void Raw32OSInit(void)

+{

+    /* Enable the CPU Cache's */

+	SCB_EnableICache();	// Enable I-Cache

+	SCB_EnableDCache();	// Enable D-Cache

+

+

+    /* STM32F7xx HAL library initialization:

+         - Configure the Flash ART accelerator on ITCM interface

+         - Configure the Systick to generate an interrupt each 1 msec

+         - Set NVIC Group Priority to 4

+         - Global MSP (MCU Support Package) initialization

+       */

+    HAL_Init();

+

+    /* Configure the system clock to 216 MHz */

+    SystemClock_Config();

+}

diff --git a/changelog.txt b/changelog.txt
index ee504df8..ef320e4c 100644
--- a/changelog.txt
+++ b/changelog.txt
@@ -64,6 +64,7 @@ FEATURE:    Added nullpointer checks to GDISP image functions (with new error co
 FIX:		Add cache flushing to the ChibiOS FATFS/PETITFS block drivers. Needed for STM32F7 chips. This should really be in the ChibiOS DMA routines.

 FIX:		Add cache flushing to enable DMA2D accelerated bitblits in the STM32LTDC driver on the STM32F7 cpu.

 FIX:		Improved STM32F469i-Discovery board support.

+FIX:		Improved STM32F746G-Discovery board support.

 

 

 *** Release 2.7 ***