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/*
     Copyright (C) Dean Camera, 2018.

  dean [at] fourwalledcubicle [dot] com
           www.lufa-lib.org
*/

#ifndef _RTC_H_
#define _RTC_H_

	/* Includes: */
		#include <avr/io.h>

		#include <LUFA/Drivers/Peripheral/TWI.h>

		#include "Config/AppConfig.h"

	/* Type Defines: */
		typedef struct
		{
			uint8_t Hour;
			uint8_t Minute;
			uint8_t Second;
			uint8_t Day;
			uint8_t Month;
			uint8_t Year;
		} TimeDate_t;

		typedef struct
		{
			union
			{
				struct
				{
					unsigned Sec            : 4;
					unsigned TenSec         : 3;
					unsigned CH             : 1;
				} Fields;

				uint8_t IntVal;
			} Byte1;

			union
			{
				struct
				{
					unsigned Min            : 4;
					unsigned TenMin         : 3;
					unsigned Reserved       : 1;
				} Fields;

				uint8_t IntVal;
			} Byte2;

			union
			{
				struct
				{
					unsigned Hour            : 4;
					unsigned TenHour         : 2;
					unsigned TwelveHourMode  : 1;
					unsigned Reserved        : 1;
				} Fields;

				uint8_t IntVal;
			} Byte3;

			union
			{
				struct
				{
					unsigned DayOfWeek       : 3;
					unsigned Reserved        : 5;
				} Fields;

				uint8_t IntVal;
			} Byte4;

			union
			{
				struct
				{
					unsigned Day             : 4;
					unsigned TenDay          : 2;
					unsigned Reserved        : 2;
				} Fields;

				uint8_t IntVal;
			} Byte5;

			union
			{
				struct
				{
					unsigned Month           : 4;
					unsigned TenMonth        : 1;
					unsigned Reserved        : 3;
				} Fields;

				uint8_t IntVal;
			} Byte6;

			union
			{
				struct
				{
					unsigned Year            : 4;
					unsigned TenYear         : 4;
				} Fields;

				uint8_t IntVal;
			} Byte7;
		} DS1307_DateTimeRegs_t;

	/* Macros: */
		/** TWI address of the DS1307 device on the bus. */
		#define DS1307_ADDRESS       0xD0

	/* Function Prototypes: */
		void RTC_Init(void);
		void RTC_Tick500ms(void);
		bool RTC_SetTimeDate(const TimeDate_t* NewTimeDate);
		bool RTC_GetTimeDate(TimeDate_t* const TimeDate);

#endif
is mostly because delaying certain elaboration steps to the runtime prevents elaboration-time optimisions. .. HINT:: Currently, GHDL has limited support for generic types in the CLI. It is suggested to use strings or integers. Nonetheless, project `JSON-for-VHDL <https://github.com/Paebbels/JSON-for-VHDL>`_ allows to encode a set of parameters as stringified JSON, and it provides VHDL functions to read specific values from it. It is valid for synthesis. .. option:: --assert-level=<LEVEL> Select the assertion level at which an assertion violation stops the simulation. `LEVEL` is the name from the `severity_level` enumerated type defined in the `standard` package or the ``none`` name. By default, only assertion violation of severity level ``failure`` stops the simulation. For example, if `LEVEL` was ``warning``, any assertion violation with severity level ``warning``, ``error`` or ``failure`` would stop simulation, but the assertion violation at the ``note`` severity level would only display a message. Option :option:`--assert-level=none <--assert-level>` prevents any assertion violation from stopping simulation. .. option:: --backtrace-severity=<LEVEL> Select the assertion level at which an assertion violation display a backtrace (if available). This is useful when the assertion is generated by a function (like assertions in ``ieee.numeric_std``) whose location is not very useful. .. option:: --ieee-asserts=<POLICY> .. option:: --asserts=<POLICY> Select how assertions are handled. `POLICY` can be ``enable`` (the default), ``disable`` which disables all assertions and ``disable-at-0`` which disables only at the start of simulation. The ``--ieee-asserts`` applies only to assertions from ``ieee`` package. This option can be useful to avoid assertion messages from ``ieee.numeric_std`` (and other ``ieee`` packages). The ``--asserts`` option applies to all assertions, including those from the ``ieee`` units. The behaviour of the latter can be overridden by using the ``--ieee-asserts`` option after the ``--asserts`` option. .. option:: --stop-time=<TIME> Stop the simulation after ``TIME``. ``TIME`` is expressed as a time value, *without* any space. The time is the simulation time, not the real clock time. For example:: $ ./my_design --stop-time=10ns $ ./my_design --stop-time=ps .. option:: --stop-delta=<N> Stop the simulation after `N` delta cycles in the same current time. The default is 5000. .. index:: display time .. option:: --disp-time Display the time and delta cycle number as simulation advances. .. option:: --unbuffered Disable buffering on stdout, stderr and files opened in write or append mode (TEXTIO). .. option:: --max-stack-alloc=<N> Emit an error message in case of allocation on the stack of an object larger than `N` KB. Use 0 to disable these checks. .. option:: --sdf=<PATH=FILENAME> Do VITAL annotation on `PATH` with SDF file :file:`FILENAME`. `PATH` is a path of instances, separated with ``.`` or ``/``. Any separator can be used. Instances are component instantiation labels, generate labels or block labels. Currently, you cannot use an indexed name. Specifying a delay:: --sdf=min=PATH=FILENAME --sdf=typ=PATH=FILENAME --sdf=max=PATH=FILENAME If the option contains a type of delay, that is ``min=``, ``typ=`` or ``max=``, the annotator use respectively minimum, typical or maximum values. If the option does not contain a type of delay, the annotator uses the typical delay. See section :ref:`Backannotation`, for more details. .. option:: --vpi=<FILENAME> Load VPI module. .. HINT:: Currently, although multiple ``--vpi=`` options can be passed, only the last one is kept/used. However, handling more than one shouldn't be a difficult change. .. option:: --vpi-trace=<FILE> Trace vpi calls to FILE. .. option:: --help Display a short description of the options accepted by the runtime library. .. option:: --no-run Stop the simulation before the first cycle. This option actually elaborates the design, so it will catch any bound error in port maps. See also :option:`-e`. This may be used with :option:`--disp-tree` to display the tree without simulating the whole design. .. _export_waves: Export waveforms ================ .. option:: --read-wave-opt=<FILENAME> Filter signals to be dumped to the wave file according to the wave option file provided. Here is a description of the wave option file format currently supported :: $ version = 1.1 # Optional # Path format for signals in packages : my_pkg.global_signal_a # Path format for signals in entities : /top/sub/clk # Dump every signal named reset in first level sub entities of top /top/*/reset # Dump every signal named reset in recursive sub entities of top /top/**/reset # Dump every signal of sub2 which could be anywhere in the design except # on the top level /**/sub2/* # Dump every signal of sub3 which must be a first level sub entity of the # top level /*/sub3/* # Dump every signal of the first level sub entities of sub3 (but not # those of sub3) /**/sub3/*/* .. option:: --write-wave-opt=<FILENAME> If the wave option file doesn't exist, creates it with all the signals of the design. Otherwise throws an error, because it won't erase an existing file. .. option:: --vcd=<FILENAME> .. option:: --vcdgz=<FILENAME> .. index:: vcd .. index:: value change dump .. index:: dump of signals Option :option:`--vcd` dumps into the VCD file `FILENAME` the signal values before each non-delta cycle. If `FILENAME` is ``-``, then the standard output is used, otherwise a file is created or overwritten. The :option:`--vcdgz` option is the same as the :option:`--vcd` option, but the output is compressed using the `zlib` (`gzip` compression). However, you can't use the ``-`` filename. Furthermore, only one VCD file can be written. :dfn:`VCD` (value change dump) is a file format defined by the `verilog` standard and used by virtually any wave viewer. Since it comes from `verilog`, only a few VHDL types can be dumped. GHDL dumps only signals whose base type is of the following: * types defined in the ``std.standard`` package: * ``bit`` * ``bit_vector`` * types defined in the ``ieee.std_logic_1164`` package: * ``std_ulogic`` * ``std_logic`` (because it is a subtype of ``std_ulogic``) * ``std_ulogic_vector`` * ``std_logic_vector`` * any integer type I have successfully used `gtkwave` to view VCD files. Currently, there is no way to select signals to be dumped: all signals are dumped, which can generate big files. It is very unfortunate there is no standard or well-known wave file format supporting VHDL types. If you are aware of such a free format, please mail me (:ref:`Reporting_bugs`). .. option:: --vcd-nodate Do not write date in the VCD file. .. option:: --fst=<FILENAME> Write the waveforms into an `fst` file that can be displayed by `gtkwave`. The `fst` files are much smaller than VCD or `GHW` files, but it handles only the same signals as the VCD format. .. option:: --wave=<FILENAME> Write the waveforms into a `ghw` (GHdl Waveform) file. Currently, all the signals are dumped into the waveform file, you cannot select a hierarchy of signals to be dumped. The format of this file was defined by myself and is not yet completely fixed. It may change slightly. The ``gtkwave`` tool can read the GHW files. Contrary to VCD files, any VHDL type can be dumped into a GHW file. Export hierarchy and references =============================== .. option:: --disp-tree=<KIND> .. index:: display design hierarchy Display the design hierarchy as a tree of instantiated design entities. This may be useful to understand the structure of a complex design. `KIND` is optional, but if set must be one of: * ``none`` Do not display hierarchy. Same as if the option was not present. * ``inst`` Display entities, architectures, instances, blocks and generates statements. * ``proc`` Like ``inst`` but also display processes. * ``port`` Like ``proc`` but display ports and signals too. If `KIND` is not specified, the hierarchy is displayed with the ``port`` mode. .. option:: --xref-html [options] files... To easily navigate through your sources, you may generate cross-references. This command generates an html file for each ``file`` given in the command line, with syntax highlighting and full cross-reference: every identifier is a link to its declaration. An index of the files is created too. The set of ``files`` are analyzed, and then, if the analysis is successful, html files are generated in the directory specified by the ``-o <DIR>`` option, or :file:`html/` directory by default. The style of the html file can be modified with the :option:`--format` option. .. option:: --psl-report=<FILENAME> Write a report for PSL at the end of simulation. For each PSL cover and assert statements, the name, source location and whether it passed or failed is reported. The file is written using the JSON format, but is still human readable.