aboutsummaryrefslogtreecommitdiffstats
path: root/Projects/AVRISP/Lib/PDITarget.c
blob: 22a4d019a4a7eca67460cc0594ac624e821a2e47 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
/*
             LUFA Library
     Copyright (C) Dean Camera, 2009.
              
  dean [at] fourwalledcubicle [dot] com
      www.fourwalledcubicle.com
*/

/*
  Copyright 2009  Dean Camera (dean [at] fourwalledcubicle [dot] com)

  Permission to use, copy, modify, and distribute this software
  and its documentation for any purpose and without fee is hereby
  granted, provided that the above copyright notice appear in all
  copies and that both that the copyright notice and this
  permission notice and warranty disclaimer appear in supporting
  documentation, and that the name of the author not be used in
  advertising or publicity pertaining to distribution of the
  software without specific, written prior permission.

  The author disclaim all warranties with regard to this
  software, including all implied warranties of merchantability
  and fitness.  In no event shall the author be liable for any
  special, indirect or consequential damages or any damages
  whatsoever resulting from loss of use, data or profits, whether
  in an action of contract, negligence or other tortious action,
  arising out of or in connection with the use or performance of
  this software.
*/

#if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)

/** \file
 *
 *  Target-related functions for the PDI Protocol decoder.
 */

#define  INCLUDE_FROM_PDITARGET_C
#include "PDITarget.h"

volatile bool     IsSending;

#if !defined(PDI_VIA_HARDWARE_USART)
volatile uint16_t DataBits;
volatile uint8_t  BitCount;

ISR(TIMER0_COMPA_vect, ISR_BLOCK)
{
	BITBANG_PDICLOCK_PORT ^= BITBANG_PDICLOCK_MASK;

	/* If not sending or receiving, just exit */
	if (!(BitCount))
	  return;
	
	/* Check to see if the current clock state is on the rising or falling edge */
	bool IsRisingEdge = (BITBANG_PDICLOCK_PORT & BITBANG_PDICLOCK_MASK);

	if (IsSending && !IsRisingEdge)
	{
		if (DataBits & 0x01)
		  BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
		else
		  BITBANG_PDIDATA_PORT |=  BITBANG_PDIDATA_MASK;		  

		DataBits >>= 1;
		BitCount--;
	}
	else if (!IsSending && IsRisingEdge)
	{
		/* Wait for the start bit when receiving */
		if ((BitCount == BITS_IN_FRAME) && (BITBANG_PDIDATA_PORT & BITBANG_PDIDATA_MASK))
		  return;
	
		if (BITBANG_PDIDATA_PORT & BITBANG_PDIDATA_MASK)
		  DataBits |= (1 << (BITS_IN_FRAME - 1));

		DataBits >>= 1;
		BitCount--;
	}
}

void PDITarget_EnableTargetPDI(void)
{
	/* Set DATA and CLOCK lines to outputs */
	BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;
	BITBANG_PDICLOCK_DDR |= BITBANG_PDICLOCK_MASK;
	
	/* Set DATA line high for 90ns to disable /RESET functionality */
	BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
	asm volatile ("NOP"::);
	asm volatile ("NOP"::);

	/* Fire timer compare ISR every 160 cycles */
	OCR0A   = 20;
	TCCR0A  = (1 << WGM01);
	TCCR0B  = (1 << CS01);
	TIMSK0  = (1 << OCIE0A);
}

void PDITarget_DisableTargetPDI(void)
{
	/* Set DATA and CLOCK lines to inputs */
	BITBANG_PDIDATA_DDR   &= ~BITBANG_PDIDATA_MASK;
	BITBANG_PDICLOCK_DDR  &= ~BITBANG_PDICLOCK_MASK;
	
	/* Tristate DATA and CLOCK lines */
	BITBANG_PDIDATA_PORT  &= ~BITBANG_PDIDATA_MASK;
	BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;

	TCCR0B  = 0;
}

void PDITarget_SendByte(uint8_t Byte)
{
	bool IsOddBitsSet = false;
	
	/* Compute Even parity bit */
	for (uint8_t i = 0; i < 8; i++)
	{
		if (Byte & (1 << i))
		  IsOddBitsSet = !(IsOddBitsSet);
	}

	/* Data shifted out LSB first, START DATA PARITY STOP STOP */
	DataBits  = ((uint16_t)IsOddBitsSet << 10) | ((uint16_t)Byte << 1) | (1 << 0);

	BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
	BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;

	IsSending = true;
	BitCount  = BITS_IN_FRAME;
	while (BitCount);

	BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
	BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;
}

uint8_t PDITarget_ReceiveByte(void)
{
	IsSending = false;
	BitCount  = BITS_IN_FRAME;
	while (BitCount);

	return (DataBits >> 1);
}

void PDITarget_SendBreak(void)
{
	DataBits  = 0;

	BITBANG_PDIDATA_PORT |= BITBANG_PDIDATA_MASK;
	BITBANG_PDIDATA_DDR  |= BITBANG_PDIDATA_MASK;

	IsSending = true;
	BitCount  = BITS_IN_FRAME;
	while (BitCount);

	BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
	BITBANG_PDIDATA_DDR  &= ~BITBANG_PDIDATA_MASK;
}
#else
void PDITarget_EnableTargetPDI(void)
{
	/* Set Tx and XCK as outputs, Rx as input */
	DDRD |=  (1 << 5) | (1 << 3);
	DDRD &= ~(1 << 2);
	
	/* Set DATA line high for 90ns to disable /RESET functionality */
	PORTD |= (1 << 3);
	asm volatile ("NOP"::);
	asm volatile ("NOP"::);
	
	/* Set up the synchronous USART for XMEGA communications - 
	   8 data bits, even parity, 2 stop bits */
	UBRR1  = 10;
	UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);

	/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
	PDITarget_SendBreak();
	PDITarget_SendBreak();
}

void PDITarget_DisableTargetPDI(void)
{
	/* Turn of receiver and transmitter of the USART, clear settings */
	UCSR1B = 0;
	UCSR1C = 0;

	/* Set all USART lines as input, tristate */
	DDRD  &= ~((1 << 5) | (1 << 3));
	PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
}

void PDITarget_SendByte(uint8_t Byte)
{
	/* Switch to Tx mode if currently in Rx mode */
	if (!(IsSending))
	{
		PORTD  |=  (1 << 3);
		DDRD   |=  (1 << 3);

		UCSR1B &= ~(1 << RXEN1);
		UCSR1B |=  (1 << TXEN1);
		
		IsSending = true;
	}
	
	/* Wait until there is space in the hardware Tx buffer before writing */
	while (!(UCSR1A & (1 << UDRE1)));
	UDR1 = Byte;
}

uint8_t PDITarget_ReceiveByte(void)
{
	/* Switch to Rx mode if currently in Tx mode */
	if (IsSending)
	{
		while (!(UCSR1A & (1 << TXC1)));
		UCSR1A |=  (1 << TXC1);

		UCSR1B &= ~(1 << TXEN1);
		UCSR1B |=  (1 << RXEN1);

		DDRD   &= ~(1 << 3);
		PORTD  &= ~(1 << 3);
		
		IsSending = false;
	}

	/* Wait until a byte has been received before reading */
	while (!(UCSR1A & (1 << RXC1)));
	return UDR1;
}

void PDITarget_SendBreak(void)
{
	/* Switch to Tx mode if currently in Rx mode */
	if (!(IsSending))
	{
		PORTD  |=  (1 << 3);
		DDRD   |=  (1 << 3);

		UCSR1B &= ~(1 << RXEN1);
		UCSR1B |=  (1 << TXEN1);
		
		IsSending = true;
	}

	/* Need to do nothing for a full frame to send a BREAK */
	for (uint8_t i = 0; i <= BITS_IN_FRAME; i++)
	{
		/* Wait for rising edge of clock */
		while (PIND & (1 << 5));
		
		/* Wait for falling edge of clock */
		while (!(PIND & (1 << 5)));
	}
}
#endif

#endif