/* $Date: 2005/10/24 23:18:13 $ $RCSfile: mv88e1xxx.c,v $ $Revision: 1.49 $ */ #include "common.h" #include "mv88e1xxx.h" #include "cphy.h" #include "elmer0.h" /* MV88E1XXX MDI crossover register values */ #define CROSSOVER_MDI 0 #define CROSSOVER_MDIX 1 #define CROSSOVER_AUTO 3 #define INTR_ENABLE_MASK 0x6CA0 /* * Set the bits given by 'bitval' in PHY register 'reg'. */ static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval) { u32 val; (void) simple_mdio_read(cphy, reg, &val); (void) simple_mdio_write(cphy, reg, val | bitval); } /* * Clear the bits given by 'bitval' in PHY register 'reg'. */ static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval) { u32 val; (void) simple_mdio_read(cphy, reg, &val); (void) simple_mdio_write(cphy, reg, val & ~bitval); } /* * NAME: phy_reset * * DESC: Reset the given PHY's port. NOTE: This is not a global * chip reset. * * PARAMS: cphy - Pointer to PHY instance data. * * RETURN: 0 - Successful reset. * -1 - Timeout. */ static int mv88e1xxx_reset(struct cphy *cphy, int wait) { u32 ctl; int time_out = 1000; mdio_set_bit(cphy, MII_BMCR, BMCR_RESET); do { (void) simple_mdio_read(cphy, MII_BMCR, &ctl); ctl &= BMCR_RESET; if (ctl) udelay(1); } while (ctl && --time_out); return ctl ? -1 : 0; } static int mv88e1xxx_interrupt_enable(struct cphy *cphy) { /* Enable PHY interrupts. */ (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, INTR_ENABLE_MASK); /* Enable Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { u32 elmer; t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); elmer |= ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) elmer |= ELMER0_GP_BIT2 | ELMER0_GP_BIT3 | ELMER0_GP_BIT4; t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); } return 0; } static int mv88e1xxx_interrupt_disable(struct cphy *cphy) { /* Disable all phy interrupts. */ (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0); /* Disable Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { u32 elmer; t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); elmer &= ~ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4); t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); } return 0; } static int mv88e1xxx_interrupt_clear(struct cphy *cphy) { u32 elmer; /* Clear PHY interrupts by reading the register. */ (void) simple_mdio_read(cphy, MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer); /* Clear Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); elmer |= ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4; t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); } return 0; } /* * Set the PHY speed and duplex. This also disables auto-negotiation, except * for 1Gb/s, where auto-negotiation is mandatory. */ static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex) { u32 ctl; (void) simple_mdio_read(phy, MII_BMCR, &ctl); if (speed >= 0) { ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); if (speed == SPEED_100) ctl |= BMCR_SPEED100; else if (speed == SPEED_1000) ctl |= BMCR_SPEED1000; } if (duplex >= 0) { ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE); if (duplex == DUPLEX_FULL) ctl |= BMCR_FULLDPLX; } if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */ ctl |= BMCR_ANENABLE; (void) simple_mdio_write(phy, MII_BMCR, ctl); return 0; } static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover) { u32 data32; (void) simple_mdio_read(cphy, MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32); data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE); data32 |= V_PSCR_MDI_XOVER_MODE(crossover); (void) simple_mdio_write(cphy, MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32); return 0; } static int mv88e1xxx_autoneg_enable(struct cphy *cphy) { u32 ctl; (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO); (void) simple_mdio_read(cphy, MII_BMCR, &ctl); /* restart autoneg for change to take effect */ ctl |= BMCR_ANENABLE | BMCR_ANRESTART; (void) simple_mdio_write(cphy, MII_BMCR, c
#
#             LUFA Library
#     Copyright (C) Dean Camera, 2019.
#
#  dean [at] fourwalledcubicle [dot] com
#           www.lufa-lib.org
#
# --------------------------------------
#         LUFA Project Makefile.
# --------------------------------------

# Run "make help" for target help.

MCU          = at90usb1287
ARCH         = AVR8
BOARD        = USBKEY
F_CPU        = 8000000
F_USB        = $(F_CPU)
OPTIMIZATION = s
TARGET       = KeyboardHostWithParser
SRC          = $(TARGET).c ConfigDescriptor.c HIDReport.c $(LUFA_SRC_USB) $(LUFA_SRC_SERIAL)
LUFA_PATH    = ../../../../LUFA
CC_FLAGS     = -DUSE_LUFA_CONFIG_HEADER -IConfig/
LD_FLAGS     =

# Default target
all:

# Include LUFA-specific DMBS extension modules
DMBS_LUFA_PATH ?= $(LUFA_PATH)/Build/LUFA
include $(DMBS_LUFA_PATH)/lufa-sources.mk
include $(DMBS_LUFA_PATH)/lufa-gcc.mk

# Include common DMBS build system modules
DMBS_PATH      ?= $(LUFA_PATH)/Build/DMBS/DMBS
include $(DMBS_PATH)/core.mk
include $(DMBS_PATH)/cppcheck.mk
include $(DMBS_PATH)/doxygen.mk
include $(DMBS_PATH)/dfu.mk
include $(DMBS_PATH)/gcc.mk
include $(DMBS_PATH)/hid.mk
include $(DMBS_PATH)/avrdude.mk
include $(DMBS_PATH)/atprogram.mk
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-25 02:11:13 +0000