3 files changed, 7 insertions, 4 deletions
diff --git a/Projects/AVRISP-MKII/Lib/ISP/ISPTarget.c b/Projects/AVRISP-MKII/Lib/ISP/ISPTarget.c
index f4e9e3d3a..d315e9d1e 100644
--- a/Projects/AVRISP-MKII/Lib/ISP/ISPTarget.c
+++ b/Projects/AVRISP-MKII/Lib/ISP/ISPTarget.c
@@ -199,7 +199,7 @@ void ISPTarget_ConfigureRescueClock(void)
 	/* Start Timer 1 to generate a 4MHz clock on the OCR1A pin */
 	TIMSK1 = 0;
 	TCNT1  = 0;
-	OCR1A  = ((F_CPU / 2 / 4000000UL) - 1);
+	OCR1A  = ((F_CPU / 2 / ISP_RESCUE_CLOCK_SPEED) - 1);
 	TCCR1A = (1 << COM1A0);
 	TCCR1B = ((1 << WGM12) | (1 << CS10));
 }
diff --git a/Projects/AVRISP-MKII/Lib/ISP/ISPTarget.h b/Projects/AVRISP-MKII/Lib/ISP/ISPTarget.h
index c467298c6..aae4c5b53 100644
--- a/Projects/AVRISP-MKII/Lib/ISP/ISPTarget.h
+++ b/Projects/AVRISP-MKII/Lib/ISP/ISPTarget.h
@@ -59,8 +59,11 @@
 		/** Low level device command to issue an extended FLASH address, for devices with other 128KB of FLASH. */
 		#define LOAD_EXTENDED_ADDRESS_CMD     0x4D
 
-		/** Macro to convert an ISP frequency to a number of timer clock cycles for the software SPI driver */
-		#define TIMER_COMP(freq) ((((F_CPU / 8) / freq) / 2) - 1)
+		/** Macro to convert an ISP frequency to a number of timer clock cycles for the software SPI driver. */
+		#define TIMER_COMP(freq)              (((F_CPU / 8) / 2 / freq) - 1)
+
+		/** ISP rescue clock speed, for clocking targets with incorrectly set fuses. */
+		#define ISP_RESCUE_CLOCK_SPEED        4000000
 
 	/* External Variables: */
 		extern bool HardwareSPIMode;
diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
index f0ef2b652..5d59f7f17 100644
--- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
+++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
@@ -79,7 +79,7 @@ void XPROGTarget_EnableTargetTPI(void)
 	DDRD &= ~(1 << 2);
 
 	/* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */
-	UBRR1  = (F_CPU / XPROG_HARDWARE_SPEED);
+	UBRR1  = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
 	UCSR1B = (1 << TXEN1);
 	UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);