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| author | Dean Camera <dean@fourwalledcubicle.com> | 2010-05-26 07:35:27 +0000 |
|---|---|---|
| committer | Dean Camera <dean@fourwalledcubicle.com> | 2010-05-26 07:35:27 +0000 |
| commit | f64e3db07ac167bf0b64bf429a53721f1848e91d (patch) | |
| tree | dc95d6669d123d8268989da02840ea5eaca2aba0 /Projects/XPLAINBridge/Lib/SoftUART.c | |
| parent | 79742c5d24929442175953c796a1834e45a93d0d (diff) | |
| download | lufa-f64e3db07ac167bf0b64bf429a53721f1848e91d.tar.gz lufa-f64e3db07ac167bf0b64bf429a53721f1848e91d.tar.bz2 lufa-f64e3db07ac167bf0b64bf429a53721f1848e91d.zip | |
Rename software USART driver globals to make the code more in line with the rest of the XPLAINBridge project.
Diffstat (limited to 'Projects/XPLAINBridge/Lib/SoftUART.c')
| -rw-r--r-- | Projects/XPLAINBridge/Lib/SoftUART.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/Projects/XPLAINBridge/Lib/SoftUART.c b/Projects/XPLAINBridge/Lib/SoftUART.c index 18d5c01bd..0591284e6 100644 --- a/Projects/XPLAINBridge/Lib/SoftUART.c +++ b/Projects/XPLAINBridge/Lib/SoftUART.c @@ -39,7 +39,8 @@ #include "SoftUART.h" -static uint8_t TX_BitsRemaining, TX_Data, RX_BitMask, RX_Data; +static uint8_t TX_BitsRemaining, TX_Data; +static uint8_t RX_BitMask, RX_Data; void SoftUART_Init(void) { @@ -50,16 +51,15 @@ void SoftUART_Init(void) EICRA = (1 << ISC01); // -ve edge EIMSK = (1 << INT0); // enable INT0 interrupt - TX_BitsRemaining = 0; // nothing to send STXPORT |= (1 << STX); // TX output STXDDR |= (1 << STX); // TX output SRXPORT |= (1 << SRX); // pullup on INT0 } -/* ISR to detect the start of a bit being sent from the transmitter. */ +/* ISR to detect the start of a bit being sent to the software UART. */ ISR(INT0_vect) { - OCR2A = TCNT2 + (BIT_TIME / 8 * 3 / 2); // scan 1.5 bits after start + OCR2A = TCNT2 + (uint16_t)((BIT_TIME / 8.0f) * 1.5f); // scan 1.5 bits after start RX_Data = 0; // clear bit storage RX_BitMask = (1 << 0); // bit mask @@ -68,12 +68,12 @@ ISR(INT0_vect) if (!(SRXPIN & (1 << SRX))) // still low { - TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit + TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit EIMSK &= ~(1 << INT0); } } -/* ISR to manage the reception of bits to the transmitter. */ +/* ISR to manage the reception of bits to the software UART. */ ISR(TIMER2_COMPA_vect) { if (RX_BitMask) @@ -89,13 +89,13 @@ ISR(TIMER2_COMPA_vect) { RingBuffer_Insert(&UARTtoUSB_Buffer, RX_Data); - TIMSK2 = (1 << OCIE2B); // enable tx and wait for start - EIMSK |= (1 << INT0); // enable START irq - EIFR = (1 << INTF0); // clear any pending + TIMSK2 = (1 << OCIE2B); // enable tx and wait for start + EIMSK |= (1 << INT0); // enable START irq + EIFR = (1 << INTF0); // clear any pending } } -/* ISR to manage the transmission of bits to the receiver. */ +/* ISR to manage the transmission of bits via the software UART. */ ISR(TIMER2_COMPB_vect) { OCR2B += BIT_TIME / 8; // next bit slice |