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| author | Dean Camera <dean@fourwalledcubicle.com> | 2011-10-30 07:43:13 +0000 |
|---|---|---|
| committer | Dean Camera <dean@fourwalledcubicle.com> | 2011-10-30 07:43:13 +0000 |
| commit | c73997429271e8566080ac8fdf21e5944c3b4c8e (patch) | |
| tree | 8c879b10de3d096f4d97881c2c59e81a9b26e57d /LUFA/Platform | |
| parent | ab43251bf926a3ce2ff42cac433dad723452bcb4 (diff) | |
| download | lufa-c73997429271e8566080ac8fdf21e5944c3b4c8e.tar.gz lufa-c73997429271e8566080ac8fdf21e5944c3b4c8e.tar.bz2 lufa-c73997429271e8566080ac8fdf21e5944c3b4c8e.zip | |
Fix error in XMEGA clock platform driver for the DFLL calibration byte order.
Diffstat (limited to 'LUFA/Platform')
| -rw-r--r-- | LUFA/Platform/XMEGA/ClockManagement.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/LUFA/Platform/XMEGA/ClockManagement.h b/LUFA/Platform/XMEGA/ClockManagement.h index 18d7c631e..07ba0e73c 100644 --- a/LUFA/Platform/XMEGA/ClockManagement.h +++ b/LUFA/Platform/XMEGA/ClockManagement.h @@ -275,19 +275,19 @@ switch (Source) { case CLOCK_SRC_INT_RC2MHZ: - OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp); - DFLLRC2M.COMP1 = (DFLLCompare >> 8); - DFLLRC2M.COMP2 = (DFLLCompare & 0xFF); - DFLLRC2M.CALA = (DFFLCal >> 8); - DFLLRC2M.CALB = (DFFLCal & 0xFF); + OSC.DFLLCTRL |= (Reference << OSC_RC2MCREF_bp); + DFLLRC2M.COMP1 = (DFLLCompare & 0xFF); + DFLLRC2M.COMP2 = (DFLLCompare >> 8); + DFLLRC2M.CALA = (DFFLCal & 0xFF); + DFLLRC2M.CALB = (DFFLCal >> 8); DFLLRC2M.CTRL = DFLL_ENABLE_bm; break; case CLOCK_SRC_INT_RC32MHZ: OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp); - DFLLRC32M.COMP1 = (DFLLCompare >> 8); - DFLLRC32M.COMP2 = (DFLLCompare & 0xFF); - DFLLRC32M.CALA = (DFFLCal >> 8); - DFLLRC32M.CALB = (DFFLCal & 0xFF); + DFLLRC32M.COMP1 = (DFLLCompare & 0xFF); + DFLLRC32M.COMP2 = (DFLLCompare >> 8); + DFLLRC32M.CALA = (DFFLCal & 0xFF); + DFLLRC32M.CALB = (DFFLCal >> 8); DFLLRC32M.CTRL = DFLL_ENABLE_bm; break; default: |