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authorDean Camera <dean@fourwalledcubicle.com>2011-10-12 02:27:22 +0000
committerDean Camera <dean@fourwalledcubicle.com>2011-10-12 02:27:22 +0000
commitc15eaa5dae5b8913d9401f0ad508494a6b66744a (patch)
tree63bdae6e1f3735ee05d662a6fb2efd51b59d5561 /LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
parent1a4a26271e32fba6e2430b7869ec4a8b4242e6e2 (diff)
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When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale).
Diffstat (limited to 'LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c')
-rw-r--r--LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c b/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
index 571ab6c8a..9f688db06 100644
--- a/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
+++ b/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
@@ -68,7 +68,7 @@ void USB_Init(
if (!(USB_Options & USB_OPT_MANUAL_PLL))
{
#if defined(USB_SERIES_4_AVR)
- PLLFRQ = ((1 << PLLUSB) | (1 << PDIV3) | (1 << PDIV1));
+ PLLFRQ = (1 << PDIV2);
#endif
}