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/*-----------------------------------------------------------------------
/  Low level disk interface module include file
/-----------------------------------------------------------------------*/

#ifndef _DISKIO_DEFINED
#define _DISKIO_DEFINED

#ifdef __cplusplus
extern "C" {
#endif

#include "integer.h"
#include "ff.h"

#include "../DataflashManager.h"


/* Status of Disk Functions */
typedef BYTE	DSTATUS;

/* Results of Disk Functions */
typedef enum {
	RES_OK = 0,		/* 0: Successful */
	RES_ERROR,		/* 1: R/W Error */
	RES_WRPRT,		/* 2: Write Protected */
	RES_NOTRDY,		/* 3: Not Ready */
	RES_PARERR		/* 4: Invalid Parameter */
} DRESULT;


/*---------------------------------------*/
/* Prototypes for disk control functions */

DSTATUS disk_initialize (BYTE);
DSTATUS disk_status (BYTE);
DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
DRESULT disk_ioctl (BYTE, BYTE, void*);


/* Disk Status Bits (DSTATUS) */

#define STA_NOINIT		0x01	/* Drive not initialized */
#define STA_NODISK		0x02	/* No medium in the drive */
#define STA_PROTECT		0x04	/* Write protected */


#ifdef __cplusplus
}
#endif

#endif
ass="gi">+#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) +#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) +#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9) +#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11) +#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) +#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) +#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14) +#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) + +#define QCA955X_MR_AN_STATUS_EXT_CAP BIT(0) +#define QCA955X_MR_AN_STATUS_LINK_UP BIT(2) +#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3) +#define QCA955X_MR_AN_STATUS_REMOTE_FAULT BIT(4) +#define QCA955X_MR_AN_STATUS_AN_COMPLETE BIT(5) +#define QCA955X_MR_AN_STATUS_NO_PREAMBLE BIT(6) +#define QCA955X_MR_AN_STATUS_BASE_PAGE BIT(7) + +#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 +#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 +#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) +#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) +#define QCA955X_SGMII_CONFIG_FORCE_SPEED BIT(5) +#define QCA955X_SGMII_CONFIG_SPEED_SHIFT 6 +#define QCA955X_SGMII_CONFIG_SPEED_MASK 0xc0 +#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) +#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) +#define QCA955X_SGMII_CONFIG_MDIO_ENABLE BIT(10) +#define QCA955X_SGMII_CONFIG_MDIO_PULSE BIT(11) +#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) +#define QCA955X_SGMII_CONFIG_PRBS_ENABLE BIT(13) +#define QCA955X_SGMII_CONFIG_BERT_ENABLE BIT(14) + +#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff +#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0 +#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff00 +#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8 +#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000 +#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 +#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf000000 +#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24 + /* * QCA956X GMAC Interface */