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path: root/lib/lufa/BuildTests/ModuleTest/Test_CPP.cpp
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/*
             LUFA Library
     Copyright (C) Dean Camera, 2017.

  dean [at] fourwalledcubicle [dot] com
           www.lufa-lib.org
*/

/*
  Copyright 2017  Dean Camera (dean [at] fourwalledcubicle [dot] com)

  Permission to use, copy, modify, distribute, and sell this
  software and its documentation for any purpose is hereby granted
  without fee, provided that the above copyright notice appear in
  all copies and that both that the copyright notice and this
  permission notice and warranty disclaimer appear in supporting
  documentation, and that the name of the author not be used in
  advertising or publicity pertaining to distribution of the
  software without specific, written prior permission.

  The author disclaims all warranties with regard to this
  software, including all implied warranties of merchantability
  and fitness.  In no event shall the author be liable for any
  special, indirect or consequential damages or any damages
  whatsoever resulting from loss of use, data or profits, whether
  in an action of contract, negligence or other tortious action,
  arising out of or in connection with the use or performance of
  this software.
*/

#include "Modules.h"
ighlight .go { color: #888888 } /* Generic.Output */ .highlight .gp { color: #555555 } /* Generic.Prompt */ .highlight .gs { font-weight: bold } /* Generic.Strong */ .highlight .gu { color: #666666 } /* Generic.Subheading */ .highlight .gt { color: #aa0000 } /* Generic.Traceback */ .highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */ .highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */ .highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */ .highlight .kp { color: #008800 } /* Keyword.Pseudo */ .highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */ .highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */ .highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */ .highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */ .highlight .na { color: #336699 } /* Name.Attribute */ .highlight .nb { color: #003388 } /* Name.Builtin */ .highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */ .highlight .no { color: #003366; font-weight: bold } /* Name.Constant */ .highlight .nd { color: #555555 } /* Name.Decorator */ .highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */ .highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */ .highlight .nl { color: #336699; font-style: italic } /* Name.Label */ .highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */ .highlight .py { color: #336699; font-weight: bold } /* Name.Property */ .highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */ .highlight .nv { color: #336699 } /* Name.Variable */ .highlight .ow { color: #008800 } /* Operator.Word */ .highlight .w { color: #bbbbbb } /* Text.Whitespace */ .highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */ .highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */ .highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */ .highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */ .highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */ .highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */ .highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */ .highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */ .highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */ .highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */ .highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */ .highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */ .highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */ .highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */ .highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */ .highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */ .highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */ .highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */ .highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */ .highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */ .highlight .vc { color: #336699 } /* Name.Variable.Class */ .highlight .vg { color: #dd7700 } /* Name.Variable.Global */ .highlight .vi { color: #3333bb } /* Name.Variable.Instance */ .highlight .vm { color: #336699 } /* Name.Variable.Magic */ .highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */
--  Elaboration for VHDL simulation
--  Copyright (C) 2022 Tristan Gingold
--
--  This file is part of GHDL.
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <gnu.org/licenses>.

with Types; use Types;
with Tables;

with Grt.Types; use Grt.Types;
with Grt.Vhdl_Types; use Grt.Vhdl_Types;

with Vhdl.Nodes; use Vhdl.Nodes;

with Elab.Memtype; use Elab.Memtype;
with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
with Elab.Vhdl_Values; use Elab.Vhdl_Values;
with Elab.Vhdl_Context; use Elab.Vhdl_Context;

package Simul.Vhdl_Elab is
   procedure Gather_Processes (Top : Synth_Instance_Acc);
   procedure Elab_Processes;

   --  For the debugger.
   Top_Instance : Synth_Instance_Acc;

   --  For each signals:
   --  * drivers (process + area), sources
   --  * sensitivity
   --  * waveform assignments
   --  * decomposition level: none, vectors, full.
   --  * force/release
   --  * need to track activity
   --  * need to track events
   procedure Elab_Drivers;

   type Process_Index_Type is new Nat32;
   type Driver_Index_Type is new Nat32;
   subtype Sensitivity_Index_Type is Driver_Index_Type;

   No_Process_Index : constant Process_Index_Type := 0;
   No_Driver_Index : constant Driver_Index_Type := 0;
   No_Sensitivity_Index : constant Sensitivity_Index_Type := 0;

   type Proc_Record_Type is record
      Proc : Node;
      Inst : Synth_Instance_Acc;
      Drivers : Driver_Index_Type;
      Sensitivity : Sensitivity_Index_Type;
   end record;

   --  Table of all processes (explicit or implicit).
   package Processes_Table is new Tables
     (Table_Component_Type => Proc_Record_Type,
      Table_Index_Type => Process_Index_Type,
      Table_Low_Bound => No_Process_Index + 1,
      Table_Initial => 128);

   type Simultaneous_Record is record
      Stmt : Node;
      Inst : Synth_Instance_Acc;
   end record;

   type Simultaneous_Index_Type is new Nat32;

   package Simultaneous_Table is new Tables
     (Table_Component_Type => Simultaneous_Record,
      Table_Index_Type => Simultaneous_Index_Type,
      Table_Low_Bound => 1,
      Table_Initial => 16);

   type Connect_Index_Type is new Nat32;
   No_Connect_Index : constant Connect_Index_Type := 0;

   type Connect_Endpoint is record
      Base : Signal_Index_Type;
      Offs : Value_Offsets;
      Typ : Type_Acc;
   end record;

   --  Connections.  For each associations (block/component/entry), the
   --  elaborator adds an entry in that table.
   type Connect_Entry is record
      Formal : Connect_Endpoint;
      --  Next connection for the formal.
      Formal_Link : Connect_Index_Type;

      Actual : Connect_Endpoint;
      --  Next connection for the actual.
      Actual_Link : Connect_Index_Type;

      --  Whether it is a source for the actual or/and the actual.
      --  The correct word is 'source'.
      Drive_Formal : Boolean;
      Drive_Actual : Boolean;

      --  If true, the connection is fully collapsed: formal is the same
      --  signal as actual.
      Collapsed : Boolean;

      Assoc : Node;
      Assoc_Inst : Synth_Instance_Acc;
   end record;

   package Connect_Table is new Tables
     (Table_Component_Type => Connect_Entry,
      Table_Index_Type => Connect_Index_Type,
      Table_Low_Bound => No_Connect_Index + 1,
      Table_Initial => 32);

   --  Signals.

   type Signal_Entry (Kind : Mode_Signal_Type := Mode_Signal) is record
      Decl : Iir;
      Inst : Synth_Instance_Acc;
      Typ : Type_Acc;
      Val : Memory_Ptr;
      Sig : Memory_Ptr;

      --  Processes sensitized by this signal.
      Sensitivity : Sensitivity_Index_Type;

      --  This signal is identical to Collapsed_By, if set.
      Collapsed_By : Signal_Index_Type;

      case Kind is
         when Mode_Signal_User =>
            Drivers : Driver_Index_Type;
            Connect : Connect_Index_Type;
         when Mode_Quiet | Mode_Stable | Mode_Delayed
           | Mode_Transaction =>
            Time : Std_Time;
            Prefix : Memory_Ptr;
         when Mode_Above =>
            null;
         when Mode_Guard =>
            null;
         when Mode_Conv_In | Mode_Conv_Out | Mode_End =>
            --  Unused.
            null;
      end case;
   end record;

   package Signals_Table is new Tables
     (Table_Component_Type => Signal_Entry,
      Table_Index_Type => Signal_Index_Type,
      Table_Low_Bound => No_Signal_Index + 1,
      Table_Initial => 128);

   type Driver_Entry is record
      --  The signal having a driver.
      Sig : Signal_Index_Type;
      Off : Value_Offsets;
      Typ : Type_Acc;
      --  Previous driver for the same signal.
      Prev_Sig : Driver_Index_Type;

      --  The process driving this signal.
      Proc : Process_Index_Type;
      --  Previous driver for the same process.
      Prev_Proc : Driver_Index_Type;
   end record;

   package Drivers_Table is new Tables
     (Table_Component_Type => Driver_Entry,
      Table_Index_Type => Driver_Index_Type,
      Table_Low_Bound => No_Driver_Index + 1,
      Table_Initial => 128);

   subtype Sensitivity_Entry is Driver_Entry;

   package Sensitivity_Table is new Tables
     (Table_Component_Type => Driver_Entry,
      Table_Index_Type => Sensitivity_Index_Type,
      Table_Low_Bound => No_Sensitivity_Index + 1,
      Table_Initial => 128);

   type Scalar_Quantity_Index is new Uns32;
   No_Scalar_Quantity : constant Scalar_Quantity_Index := 0;

   type Quantity_Entry is record
      Decl : Iir;
      Inst : Synth_Instance_Acc;
      Typ : Type_Acc;
      Val : Memory_Ptr;
      --  Index in the scalar table.
      Idx : Scalar_Quantity_Index;
      --  For across quantity, we need the terminals to compute the value
      --  For a through quantity, we need the terminals to compute the contrib
   end record;

   package Quantity_Table is new Tables
     (Table_Component_Type => Quantity_Entry,
      Table_Index_Type => Quantity_Index_Type,
      Table_Low_Bound => No_Quantity_Index + 1,
      Table_Initial => 128);

   type Scalar_Terminal_Index is new Uns32;
   No_Scalar_Terminal : constant Scalar_Terminal_Index := 0;

   type Terminal_Entry is record
      Decl : Iir;
      Inst : Synth_Instance_Acc;
      Across_Typ : Type_Acc;
      Through_Typ : Type_Acc;
      --  The reference value.
      Ref_Val : Memory_Ptr;
      --  Index in the scalar quantity table for the reference value.
      Ref_Idx : Scalar_Quantity_Index;
      --  Index in the scalar terminal table for the contribution.
      Term_Idx : Scalar_Terminal_Index;
   end record;

   package Terminal_Table is new Tables
     (Table_Component_Type => Terminal_Entry,
      Table_Index_Type => Terminal_Index_Type,
      Table_Low_Bound => No_Terminal_Index + 1,
      Table_Initial => 32);
end Simul.Vhdl_Elab;