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{
  "keyboard_name": "Planck Light",
  "keyboard_folder": "planck/light",
  "url": "https://olkb.com/planck",
  "maintainer": "jackhumbert",
  "width": 12,
  "height": 4,
  "layouts": {
    "LAYOUT_planck_1x2uC": {
      "key_count": 47,
      "layout": [
        { "x": 0, "y": 0 },
        { "x": 1, "y": 0 },
        { "x": 2, "y": 0 },
        { "x": 3, "y": 0 },
        { "x": 4, "y": 0 },
        { "x": 5, "y": 0 },
        { "x": 6, "y": 0 },
        { "x": 7, "y": 0 },
        { "x": 8, "y": 0 },
        { "x": 9, "y": 0 },
        { "x": 10, "y": 0 },
        { "x": 11, "y": 0 },
        { "x": 0, "y": 1 },
        { "x": 1, "y": 1 },
        { "x": 2, "y": 1 },
        { "x": 3, "y": 1 },
        { "x": 4, "y": 1 },
        { "x": 5, "y": 1 },
        { "x": 6, "y": 1 },
        { "x": 7, "y": 1 },
        { "x": 8, "y": 1 },
        { "x": 9, "y": 1 },
        { "x": 10, "y": 1 },
        { "x": 11, "y": 1 },
        { "x": 0, "y": 2 },
        { "x": 1, "y": 2 },
        { "x": 2, "y": 2 },
        { "x": 3, "y": 2 },
        { "x": 4, "y": 2 },
        { "x": 5, "y": 2 },
        { "x": 6, "y": 2 },
        { "x": 7, "y": 2 },
        { "x": 8, "y": 2 },
        { "x": 9, "y": 2 },
        { "x": 10, "y": 2 },
        { "x": 11, "y": 2 },
        { "x": 0, "y": 3 },
        { "x": 1, "y": 3 },
        { "x": 2, "y": 3 },
        { "x": 3, "y": 3 },
        { "x": 4, "y": 3 },
        { "x": 5, "y": 3, "w": 2 },
        { "x": 7, "y": 3 },
        { "x": 8, "y": 3 },
        { "x": 9, "y": 3 },
        { "x": 10, "y": 3 },
        { "x": 11, "y": 3 }
      ]
    },
    "LAYOUT_ortho_4x12": {
      "key_count": 48,
      "layout": [
        { "x": 0, "y": 0 },
        { "x": 1, "y": 0 },
        { "x": 2, "y": 0 },
        { "x": 3, "y": 0 },
        { "x": 4, "y": 0 },
        { "x": 5, "y": 0 },
        { "x": 6, "y": 0 },
        { "x": 7, "y": 0 },
        { "x": 8, "y": 0 },
        { "x": 9, "y": 0 },
        { "x": 10, "y": 0 },
        { "x": 11, "y": 0 },
        { "x": 0, "y": 1 },
        { "x": 1, "y": 1 },
        { "x": 2, "y": 1 },
        { "x": 3, "y": 1 },
        { "x": 4, "y": 1 },
        { "x": 5, "y": 1 },
        { "x": 6, "y": 1 },
        { "x": 7, "y": 1 },
        { "x": 8, "y": 1 },
        { "x": 9, "y": 1 },
        { "x": 10, "y": 1 },
        { "x": 11, "y": 1 },
        { "x": 0, "y": 2 },
        { "x": 1, "y": 2 },
        { "x": 2, "y": 2 },
        { "x": 3, "y": 2 },
        { "x": 4, "y": 2 },
        { "x": 5, "y": 2 },
        { "x": 6, "y": 2 },
        { "x": 7, "y": 2 },
        { "x": 8, "y": 2 },
        { "x": 9, "y": 2 },
        { "x": 10, "y": 2 },
        { "x": 11, "y": 2 },
        { "x": 0, "y": 3 },
        { "x": 1, "y": 3 },
        { "x": 2, "y": 3 },
        { "x": 3, "y": 3 },
        { "x": 4, "y": 3 },
        { "x": 5, "y": 3 },
        { "x": 6, "y": 3 },
        { "x": 7, "y": 3 },
        { "x": 8, "y": 3 },
        { "x": 9, "y": 3 },
        { "x": 10, "y": 3 },
        { "x": 11, "y": 3 }
      ]
    }
  }
}
class="o">== !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate endmodule module FDSE (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; generate case (|IS_C_INVERTED) 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate endmodule module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate endmodule module FDPE (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate endmodule