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/*
Copyright 2014 Ralf Schmitt <ralf@bunkertor.net>

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

#include <stdint.h>
#include <stdbool.h>
#include <avr/io.h>
#include <util/delay.h>
#include "print.h"
#include "debug.h"
#include "util.h"
#include "matrix.h"
#include "backlight.h"


#ifndef DEBOUNCE
#   define DEBOUNCE 5
#endif
static uint8_t debouncing = DEBOUNCE;

/* matrix state(1:on, 0:off) */
static matrix_row_t matrix[MATRIX_ROWS];
static matrix_row_t matrix_debouncing[MATRIX_ROWS];

static uint16_t read_inputs(void);
static void init_inputs(void);
static void init_outputs(void);
static void reset_inputs(void);
static void reset_outputs(void);
static void select_output(uint8_t col);

inline
uint8_t matrix_rows(void)
{
    return MATRIX_ROWS;
}

inline
uint8_t matrix_cols(void)
{
    return MATRIX_COLS;
}

void matrix_init(void)
{
    backlight_init_ports();
    init_inputs();
    init_outputs();

    for (uint8_t i=0; i < MATRIX_ROWS; i++) {
        matrix[i] = 0;
        matrix_debouncing[i] = 0;
    }
}

uint8_t matrix_scan(void)
{
    for (uint8_t col = 0; col < MATRIX_COLS; col++) {
        reset_inputs();
        reset_outputs();
        select_output(col);
        _delay_us(3);
        uint16_t rows = read_inputs();
        for (uint8_t row = 0; row < MATRIX_ROWS; row++) {
            bool prev_bit = matrix_debouncing[row] & ((matrix_row_t)1<<col);
            bool curr_bit = rows & (1<<row);
            if (prev_bit != curr_bit) {
                matrix_debouncing[row] ^= ((matrix_row_t)1<<col);
                if (debouncing) {
                    dprint("bounce!: "); dprintf("%02X", debouncing); dprintln();
                }
                debouncing = DEBOUNCE;
            }
        }
    }

    if (debouncing) {
        if (--debouncing) {
            _delay_ms(1);
        } else {
            for (uint8_t i = 0; i < MATRIX_ROWS; i++) {
                matrix[i] = matrix_debouncing[i];
            }
        }
    }

    return 1;
}

bool matrix_is_modified(void)
{
    if (debouncing) return false;
    return true;
}

inline
bool matrix_is_on(uint8_t row, uint8_t col)
{
    return (matrix[row] & ((matrix_row_t)1<<col));
}

inline
matrix_row_t matrix_get_row(uint8_t row)
{
    return matrix[row];
}

void matrix_print(void)
{
    print("\nr/c 0123456789ABCDEF\n");
    for (uint8_t row = 0; row < MATRIX_ROWS; row++) {
        phex(row); print(": ");
        pbin_reverse16(matrix_get_row(row));
        print("\n");
    }
}

uint8_t matrix_key_count(void)
{
    uint8_t count = 0;
    for (uint8_t i = 0; i < MATRIX_ROWS; i++) {
        count += bitpop16(matrix[i]);
    }
    return count;
}

static void init_inputs(void)
{
    DDRE &= ~0b01000000; // PE6 (Col 0)
    DDRB &= ~0b00001111; // PB0 (Col 1), PB1 (Col 2), PB2 (Col 3), PB3 (Col 4)
    DDRF &= ~0b00000001; // PF0 (Col 5)
    DDRD &= ~0b00100011; // PD0 (Col 6), PD1 (Col 8 TKL), PD5 (Col 7)
}

static uint16_t read_inputs(void)
{
    return (PINE&(1<<6) ? 0 : (1<<0)) |  // PE6 (Col 0)
           (PINB&(1<<0) ? 0 : (1<<1)) |  // PB0 (Col 1)
           (PINB&(1<<1) ? 0 : (1<<2)) |  // PB1 (Col 2)
           (PINB&(1<<2) ? 0 : (1<<3)) |  // PB2 (Col 3)
           (PINB&(1<<3) ? 0 : (1<<4)) |  // PB3 (Col 4)
           (PINF&(1<<0) ? 0 : (1<<5)) |  // PF0 (Col 5)
           (PIND&(1<<0) ? 0 : (1<<6)) |  // PD0 (Col 6)
           (PIND&(1<<5) ? 0 : (1<<7)) |  // PD5 (Col 7)
           (PIND&(1<<1) ? 0 : (1<<8));   // PD1 (Col 8 TKL)
}

static void reset_inputs(void)
{
    PORTE |= 0b01000000; // PE6 (Col 0)
    PORTB |= 0b00001111; // PB0 (Col 1), PB1 (Col 2), PB2 (Col 3), PB3 (Col 4)
    PORTF |= 0b00000001; // PF0 (Col 5)
    PORTD |= 0b00100011; // PD0 (Col 6), PD1 (Col 8 TKL), PD5 (Col 7)
}

static void init_outputs(void)
{
    DDRB |= 0b00010000; // PB4 (Row 0)
    DDRE |= 0b00000100; // PE2 (Row 1)
    DDRF |= 0b11110010; // PF4 (Row 2), PF7 (Row 3), PF1 (Row 4), PF6 (Row 5), PF5 (Row 7)
    DDRC |= 0b11000000; // PC6 (Row 6), PC7 (Row 9)
    DDRD |= 0b10000000; // PD7 (Row 8)
}

static void reset_outputs(void)
{
    PORTB |= 0b00010000; // PB4 (Row 0)
    PORTE |= 0b00000100; // PE2 (Row 1)
    PORTF |= 0b11110010; // PF4 (Row 2), PF7 (Row 3), PF1 (Row 4), PF6 (Row 5), PF5 (Row 7)
    PORTC |= 0b11000000; // PC6 (Row 6), PC7 (Row 9)
    PORTD |= 0b10000000; // PD7 (Row 8)
}

static void select_output(uint8_t col)
{
    switch (col) {
        case 0:
            PORTB &= ~(1<<4);
            break;
        case 1:
            PORTE &= ~(1<<2);
            break;
        case 2:
            PORTF &= ~(1<<4);
            break;
        case 3:
            PORTF &= ~(1<<7);
            break;
        case 4:
            PORTF &= ~(1<<1);
            break;
        case 5:
            PORTF &= ~(1<<6);
            break;
        case 6:
            PORTC &= ~(1<<6);
            break;
        case 7:
            PORTF &= ~(1<<5);
            break;
        case 8:
            PORTD &= ~(1<<7);
            break;
        case 9:
            PORTC &= ~(1<<7);
            break;
    }
}
>] = '\0'; if ( strcmp("XenVMMXenVMM", signature) || (eax < 0x40000002) ) { printf("FATAL: Xen hypervisor not detected\n"); __asm__ __volatile__( "ud2" ); } /* Fill in hypercall transfer pages. */ cpuid(0x40000002, &eax, &ebx, &ecx, &edx); for ( i = 0; i < eax; i++ ) wrmsr(ebx, HYPERCALL_PHYSICAL_ADDRESS + (i << 12) + i); /* Print version information. */ cpuid(0x40000001, &eax, &ebx, &ecx, &edx); hypercall_xen_version(XENVER_extraversion, extraversion); printf("Detected Xen v%u.%u%s\n", eax >> 16, eax & 0xffff, extraversion); } static void apic_setup(void) { /* Set the IOAPIC ID to tha static value used in the MP/ACPI tables. */ ioapic_write(0x00, IOAPIC_ID); /* Set up Virtual Wire mode. */ lapic_write(APIC_SPIV, APIC_SPIV_APIC_ENABLED | 0xFF); lapic_write(APIC_LVT0, APIC_MODE_EXTINT << 8); lapic_write(APIC_LVT1, APIC_MODE_NMI << 8); } static void pci_setup(void) { uint32_t base, devfn, bar_reg, bar_data, bar_sz, cmd; uint16_t class, vendor_id, device_id; unsigned int bar, pin, link, isa_irq; /* Resources assignable to PCI devices via BARs. */ struct resource { uint32_t base, max; } *resource; struct resource mem_resource = { 0xf0000000, 0xfc000000 }; struct resource io_resource = { 0xc000, 0x10000 }; /* Create a list of device BARs in descending order of size. */ struct bars { uint32_t devfn, bar_reg, bar_sz; } *bars = (struct bars *)0xc0000; unsigned int i, nr_bars = 0; /* Program PCI-ISA bridge with appropriate link routes. */ isa_irq = 0; for ( link = 0; link < 4; link++ ) { do { isa_irq = (isa_irq + 1) & 15; } while ( !(PCI_ISA_IRQ_MASK & (1U << isa_irq)) ); pci_writeb(PCI_ISA_DEVFN, 0x60 + link, isa_irq); printf("PCI-ISA link %u routed to IRQ%u\n", link, isa_irq); } /* Program ELCR to match PCI-wired IRQs. */ outb(0x4d0, (uint8_t)(PCI_ISA_IRQ_MASK >> 0)); outb(0x4d1, (uint8_t)(PCI_ISA_IRQ_MASK >> 8)); /* Scan the PCI bus and map resources. */ for ( devfn = 0; devfn < 128; devfn++ ) { class = pci_readw(devfn, PCI_CLASS_DEVICE); vendor_id = pci_readw(devfn, PCI_VENDOR_ID); device_id = pci_readw(devfn, PCI_DEVICE_ID); if ( (vendor_id == 0xffff) && (device_id == 0xffff) ) continue; ASSERT((devfn != PCI_ISA_DEVFN) || ((vendor_id == 0x8086) && (device_id == 0x7000))); switch ( class ) { case 0x0680: ASSERT((vendor_id == 0x8086) && (device_id == 0x7113)); /* * PIIX4 ACPI PM. Special device with special PCI config space. * No ordinary BARs. */ pci_writew(devfn, 0x20, 0x0000); /* No smb bus IO enable */ pci_writew(devfn, 0x22, 0x0000); pci_writew(devfn, 0x3c, 0x0009); /* Hardcoded IRQ9 */ pci_writew(devfn, 0x3d, 0x0001); break; case 0x0101: /* PIIX3 IDE */ ASSERT((vendor_id == 0x8086) && (device_id == 0x7010)); pci_writew(devfn, 0x40, 0x8000); /* enable IDE0 */ pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */ /* fall through */ default: /* Default memory mappings. */ for ( bar = 0; bar < 7; bar++ ) { bar_reg = PCI_BASE_ADDRESS_0 + 4*bar; if ( bar == 6 ) bar_reg = PCI_ROM_ADDRESS; bar_data = pci_readl(devfn, bar_reg); pci_writel(devfn, bar_reg, ~0); bar_sz = pci_readl(devfn, bar_reg); pci_writel(devfn, bar_reg, bar_data); if ( bar_sz == 0 ) continue; bar_sz &= (((bar_data & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) ? PCI_BASE_ADDRESS_MEM_MASK : (PCI_BASE_ADDRESS_IO_MASK & 0xffff)); bar_sz &= ~(bar_sz - 1); for ( i = 0; i < nr_bars; i++ ) if ( bars[i].bar_sz < bar_sz ) break; if ( i != nr_bars ) memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars)); bars[i].devfn = devfn; bars[i].bar_reg = bar_reg; bars[i].bar_sz = bar_sz; nr_bars++; } break; } /* Map the interrupt. */ pin = pci_readb(devfn, PCI_INTERRUPT_PIN); if ( pin != 0 ) { /* This is the barber's pole mapping used by Xen. */ link = ((pin - 1) + (devfn >> 3)) & 3; isa_irq = pci_readb(PCI_ISA_DEVFN, 0x60 + link); pci_writeb(devfn, PCI_INTERRUPT_LINE, isa_irq); printf("pci dev %02x:%x INT%c->IRQ%u\n", devfn>>3, devfn&7, 'A'+pin-1, isa_irq); } } /* Assign iomem and ioport resources in descending order of size. */ for ( i = 0; i < nr_bars; i++ ) { devfn = bars[i].devfn; bar_reg = bars[i].bar_reg; bar_sz = bars[i].bar_sz; bar_data = pci_readl(devfn, bar_reg); if ( (bar_data & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY ) { resource = &mem_resource; bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK; } else { resource = &io_resource; bar_data &= ~PCI_BASE_ADDRESS_IO_MASK; } base = (resource->base + bar_sz - 1) & ~(bar_sz - 1); bar_data |= base; base += bar_sz; if ( (base < resource->base) || (base > resource->max) ) { printf("pci dev %02x:%x bar %02x size %08x: no space for " "resource!\n", devfn>>3, devfn&7, bar_reg, bar_sz); continue; } resource->base = base; pci_writel(devfn, bar_reg, bar_data); printf("pci dev %02x:%x bar %02x size %08x: %08x\n", devfn>>3, devfn&7, bar_reg, bar_sz, bar_data); /* Now enable the memory or I/O mapping. */ cmd = pci_readw(devfn, PCI_COMMAND); if ( (bar_reg == PCI_ROM_ADDRESS) || ((bar_data & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) ) cmd |= PCI_COMMAND_MEMORY; else cmd |= PCI_COMMAND_IO; pci_writew(devfn, PCI_COMMAND, cmd); } } /* * If the network card is in the boot order, load the Etherboot option ROM. * Read the boot order bytes from CMOS and check if any of them are 0x4. */ static int must_load_nic(void) { uint8_t boot_order; /* Read CMOS register 0x3d (boot choices 0 and 1). */ boot_order = cmos_inb(0x3d); if ( ((boot_order & 0xf) == 0x4) || ((boot_order & 0xf0) == 0x40) ) return 1; /* Read CMOS register 0x38 (boot choice 2 and FDD test flag). */ boot_order = cmos_inb(0x38); return ((boot_order & 0xf0) == 0x40); } static int must_load_extboot(void) { return (inb(0x404) == 1); } /* Replace possibly erroneous memory-size CMOS fields with correct values. */ static void cmos_write_memory_size(void) { struct e820entry *map = HVM_E820; int i, nr = *HVM_E820_NR; uint32_t base_mem = 640, ext_mem = 0, alt_mem = 0; for ( i = 0; i < nr; i++ ) if ( (map[i].addr >= 0x100000) && (map[i].type == E820_RAM) ) break; if ( i != nr ) { alt_mem = ext_mem = map[i].addr + map[i].size; ext_mem = (ext_mem > 0x0100000) ? (ext_mem - 0x0100000) >> 10 : 0; if ( ext_mem > 0xffff ) ext_mem = 0xffff; alt_mem = (alt_mem > 0x1000000) ? (alt_mem - 0x1000000) >> 16 : 0; } /* All BIOSes: conventional memory (CMOS *always* reports 640kB). */ cmos_outb(0x15, (uint8_t)(base_mem >> 0)); cmos_outb(0x16, (uint8_t)(base_mem >> 8)); /* All BIOSes: extended memory (1kB chunks above 1MB). */ cmos_outb(0x17, (uint8_t)( ext_mem >> 0)); cmos_outb(0x18, (uint8_t)( ext_mem >> 8)); cmos_outb(0x30, (uint8_t)( ext_mem >> 0)); cmos_outb(0x31, (uint8_t)( ext_mem >> 8)); /* Some BIOSes: alternative extended memory (64kB chunks above 16MB). */ cmos_outb(0x34, (uint8_t)( alt_mem >> 0)); cmos_outb(0x35, (uint8_t)( alt_mem >> 8)); } int main(void) { int acpi_sz = 0, vgabios_sz = 0, etherboot_sz = 0, rombios_sz, smbios_sz; int extboot_sz = 0; printf("HVM Loader\n"); init_hypercalls(); printf("Writing SMBIOS tables ...\n"); smbios_sz = hvm_write_smbios_tables(); printf("Loading ROMBIOS ...\n"); rombios_sz = sizeof(rombios); if ( rombios_sz > 0x10000 ) rombios_sz = 0x10000; memcpy((void *)ROMBIOS_PHYSICAL_ADDRESS, rombios, rombios_sz); highbios_setup(); apic_setup(); pci_setup(); if ( (get_vcpu_nr() > 1) || get_apic_mode() ) create_mp_tables(); if ( cirrus_check() ) { printf("Loading Cirrus VGABIOS ...\n"); memcpy((void *)VGABIOS_PHYSICAL_ADDRESS, vgabios_cirrusvga, sizeof(vgabios_cirrusvga)); vgabios_sz = sizeof(vgabios_cirrusvga); } else { printf("Loading Standard VGABIOS ...\n"); memcpy((void *)VGABIOS_PHYSICAL_ADDRESS, vgabios_stdvga, sizeof(vgabios_stdvga)); vgabios_sz = sizeof(vgabios_stdvga); } if ( must_load_nic() ) { printf("Loading ETHERBOOT ...\n"); memcpy((void *)ETHERBOOT_PHYSICAL_ADDRESS, etherboot, sizeof(etherboot)); etherboot_sz = sizeof(etherboot); } if ( must_load_extboot() ) { printf("Loading EXTBOOT ...\n"); memcpy((void *)EXTBOOT_PHYSICAL_ADDRESS, extboot, sizeof(extboot)); extboot_sz = sizeof(extboot); } if ( get_acpi_enabled() ) { printf("Loading ACPI ...\n"); acpi_sz = acpi_build_tables((uint8_t *)ACPI_PHYSICAL_ADDRESS); ASSERT((ACPI_PHYSICAL_ADDRESS + acpi_sz) <= 0xF0000); } cmos_write_memory_size(); printf("BIOS map:\n"); if ( vgabios_sz ) printf(" %05x-%05x: VGA BIOS\n", VGABIOS_PHYSICAL_ADDRESS, VGABIOS_PHYSICAL_ADDRESS + vgabios_sz - 1); if ( etherboot_sz ) printf(" %05x-%05x: Etherboot ROM\n", ETHERBOOT_PHYSICAL_ADDRESS, ETHERBOOT_PHYSICAL_ADDRESS + etherboot_sz - 1); if ( extboot_sz ) printf(" %05x-%05x: Extboot ROM\n", EXTBOOT_PHYSICAL_ADDRESS, EXTBOOT_PHYSICAL_ADDRESS + extboot_sz - 1); if ( use_vmxassist() ) printf(" %05x-%05x: VMXAssist\n", VMXASSIST_PHYSICAL_ADDRESS, VMXASSIST_PHYSICAL_ADDRESS + sizeof(vmxassist) - 1); if ( smbios_sz ) printf(" %05x-%05x: SMBIOS tables\n", SMBIOS_PHYSICAL_ADDRESS, SMBIOS_PHYSICAL_ADDRESS + smbios_sz - 1); if ( acpi_sz ) printf(" %05x-%05x: ACPI tables\n", ACPI_PHYSICAL_ADDRESS, ACPI_PHYSICAL_ADDRESS + acpi_sz - 1); if ( rombios_sz ) printf(" %05x-%05x: Main BIOS\n", ROMBIOS_PHYSICAL_ADDRESS, ROMBIOS_PHYSICAL_ADDRESS + rombios_sz - 1); if ( use_vmxassist() ) { printf("Loading VMXAssist ...\n"); memcpy((void *)VMXASSIST_PHYSICAL_ADDRESS, vmxassist, sizeof(vmxassist)); printf("VMX go ...\n"); __asm__ __volatile__( "jmp *%%eax" : : "a" (VMXASSIST_PHYSICAL_ADDRESS), "d" (0) ); } printf("Invoking ROMBIOS ...\n"); return 0; } /* * Local variables: * mode: C * c-set-style: "BSD" * c-basic-offset: 4 * tab-width: 4 * indent-tabs-mode: nil * End: */