avr/qmk/firmware - [no description]

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author	Mathias Andersson <wraul@dbox.se>	2017-06-17 19:41:55 +0200
committer	Mathias Andersson <wraul@dbox.se>	2017-06-23 12:07:18 +0200
commit	3522496f24a3e5c13bca573f3ea1e2a17839c274 (patch)
tree	a1aa69cc907e48ea609d46d56f23ec1a6420ac33 /lib/lufa
parent	67b8bf8f70303741027575428a53513c6610d22c (diff)
download	firmware-3522496f24a3e5c13bca573f3ea1e2a17839c274.tar.gz firmware-3522496f24a3e5c13bca573f3ea1e2a17839c274.tar.bz2 firmware-3522496f24a3e5c13bca573f3ea1e2a17839c274.zip

Update Phantom config to better match template

Diffstat (limited to 'lib/lufa')

0 files changed, 0 insertions, 0 deletions

#include <xen/config.h> #include <xen/init.h> #include <xen/kernel.h> #include <xen/string.h> #include <xen/bitops.h> #include <xen/smp.h> #include <asm/processor.h> #include <asm/msr.h> #include <asm/uaccess.h> #include <asm/mpspec.h> #include <asm/apic.h> #include <mach_apic.h> #include <asm/hvm/support.h> #include "cpu.h" #define select_idle_routine(x) ((void)0) extern int trap_init_f00f_bug(void); /* * opt_cpuid_mask_ecx/edx: cpuid.1[ecx, edx] feature mask. * For example, E8400[Intel Core 2 Duo Processor series] ecx = 0x0008E3FD, * edx = 0xBFEBFBFF when executing CPUID.EAX = 1 normally. If you want to * 'rev down' to E8400, you can set these values in these Xen boot parameters. */ static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx; integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx); integer_param("cpuid_mask_edx", opt_cpuid_mask_edx); #ifdef CONFIG_X86_INTEL_USERCOPY /* * Alignment at which movsl is preferred for bulk memory copies. */ struct movsl_mask movsl_mask __read_mostly; #endif static void __devinit set_cpuidmask(void) { unsigned int eax, ebx, ecx, edx, model; if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx)) return; cpuid(0x00000001, &eax, &ebx, &ecx, &edx); model = ((eax & 0xf0000) >> 12) | ((eax & 0xf0) >> 4); if (!((model == 0x1d) || ((model == 0x17) && ((eax & 0xf) >= 4)))) { printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n", smp_processor_id()); return; } wrmsr(MSR_IA32_CPUID_FEATURE_MASK1, opt_cpuid_mask_ecx ? : ~0u, opt_cpuid_mask_edx ? : ~0u); } void __devinit early_intel_workaround(struct cpuinfo_x86 *c) { if (c->x86_vendor != X86_VENDOR_INTEL) return; /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ if (c->x86 == 15 && c->x86_cache_alignment == 64) c->x86_cache_alignment = 128; } /* * Early probe support logic for ppro memory erratum #50 * * This is called before we do cpu ident work */ int __devinit ppro_with_ram_bug(void) { /* Uses data from early_cpu_detect now */ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 1 && boot_cpu_data.x86_mask < 8) { printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); return 1; } return 0; } /* * P4 Xeon errata 037 workaround. * Hardware prefetcher may cause stale data to be loaded into the cache. */ static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c) { unsigned long lo, hi; if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { rdmsr (MSR_IA32_MISC_ENABLE, lo, hi); if ((lo & (1<<9)) == 0) { printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); lo |= (1<<9); /* Disable hw prefetching */ wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); } } } /* * find out the number of processor cores on the die */ static int __devinit num_cpu_cores(struct cpuinfo_x86 *c) { unsigned int eax, ebx, ecx, edx; if (c->cpuid_level < 4) return 1; /* Intel has a non-standard dependency on %ecx for this CPUID level. */ cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); if (eax & 0x1f) return ((eax >> 26) + 1); else return 1; } static void __devinit init_intel(struct cpuinfo_x86 *c) { unsigned int l2 = 0; char *p = NULL; #ifdef CONFIG_X86_F00F_BUG /* * All current models of Pentium and Pentium with MMX technology CPUs * have the F0 0F bug, which lets nonprivileged users lock up the system. * Note that the workaround only should be initialized once... */ c->f00f_bug = 0; if ( c->x86 == 5 ) { static int f00f_workaround_enabled = 0; c->f00f_bug = 1; if ( !f00f_workaround_enabled ) { trap_init_f00f_bug(); printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); f00f_workaround_enabled = 1; } } #endif select_idle_routine(c); l2 = init_intel_cacheinfo(c); /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */ if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) clear_bit(X86_FEATURE_SEP, c->x86_capability); /* Names for the Pentium II/Celeron processors detectable only by also checking the cache size. Dixon is NOT a Celeron. */ if (c->x86 == 6) { switch (c->x86_model) { case 5: if (c->x86_mask == 0) { if (l2 == 0) p = "Celeron (Covington)"; else if (l2 == 256)


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