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/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

#include <string.h>
#include <stdio.h>

#include "ch.h"
#include "hal.h"
#include "test.h"
#include "console.h"

/*
 * Simulator main.
 */
int main(int argc, char *argv[]) {
  msg_t result;

  (void)argc;
  (void)argv;

  /*
   * System initializations.
   * - HAL initialization, this also initializes the configured device drivers
   *   and performs the board-specific initializations.
   * - Kernel initialization, the main() function becomes a thread and the
   *   RTOS is active.
   */
  halInit();
  conInit();
  chSysInit();

  result = TestThread(&CD1);
  if (result)
    exit(1);
  else
    exit(0);
}
YOSYS_NAMESPACE_BEGIN namespace VERILOG_FRONTEND { // this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser extern struct AST::AstNode *current_ast; // this function converts a Verilog constant to an AST_CONSTANT node AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false); // names of locally typedef'ed types in a stack typedef std::map<std::string, AST::AstNode*> UserTypeMap; extern std::vector<UserTypeMap> user_type_stack; // names of package typedef'ed types extern dict<std::string, AST::AstNode*> pkg_user_types; // state of `default_nettype extern bool default_nettype_wire; // running in SystemVerilog mode extern bool sv_mode; // running in -formal mode extern bool formal_mode; // running in -noassert mode extern bool noassert_mode; // running in -noassume mode extern bool noassume_mode; // running in -norestrict mode extern bool norestrict_mode; // running in -assume-asserts mode extern bool assume_asserts_mode; // running in -assert-assumes mode extern bool assert_assumes_mode; // running in -lib mode extern bool lib_mode; // running in -specify mode extern bool specify_mode; // lexer input stream extern std::istream *lexin; } YOSYS_NAMESPACE_END // the usual bison/flex stuff extern int frontend_verilog_yydebug; void frontend_verilog_yyerror(char const *fmt, ...); void frontend_verilog_yyrestart(FILE *f); int frontend_verilog_yyparse(void); int frontend_verilog_yylex_destroy(void); int frontend_verilog_yyget_lineno(void); void frontend_verilog_yyset_lineno (int); #endif