1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
|
/*
ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ports/ARMCM3-STM32F103/stm32_serial.c
* @brief STM32F103 Serial driver code.
* @addtogroup STM32F103_SERIAL
* @{
*/
#include <ch.h>
#include "board.h"
#include "nvic.h"
#include "stm32_serial.h"
#include "stm32lib/stm32f10x_nvic.h"
#if USE_STM32_USART1 || defined(__DOXYGEN__)
/** @brief USART1 serial driver identifier.*/
FullDuplexDriver COM1;
static uint8_t ib1[SERIAL_BUFFERS_SIZE];
static uint8_t ob1[SERIAL_BUFFERS_SIZE];
#endif
#if USE_STM32_USART2 || defined(__DOXYGEN__)
/** @brief USART2 serial driver identifier.*/
FullDuplexDriver COM2;
static uint8_t ib2[SERIAL_BUFFERS_SIZE];
static uint8_t ob2[SERIAL_BUFFERS_SIZE];
#endif
#if USE_STM32_USART3 || defined(__DOXYGEN__)
/** @brief USART3 serial driver identifier.*/
FullDuplexDriver COM3;
static uint8_t ib3[SERIAL_BUFFERS_SIZE];
static uint8_t ob3[SERIAL_BUFFERS_SIZE];
#endif
/**
* @brief Error handling routine.
* @param[in] sr USART SR register value
* @param[in] com communication channel associated to the USART
*/
static void SetError(uint16_t sr, FullDuplexDriver *com) {
dflags_t sts = 0;
if (sr & SR_ORE)
sts |= SD_OVERRUN_ERROR;
if (sr & SR_PE)
sts |= SD_PARITY_ERROR;
if (sr & SR_FE)
sts |= SD_FRAMING_ERROR;
if (sr & SR_LBD)
sts |= SD_BREAK_DETECTED;
chSysLockFromIsr();
chFDDAddFlagsI(com, sts);
chSysUnlockFromIsr();
}
/**
* @brief Common IRQ handler.
* @param[in] u pointer to an USART I/O block
* @param[in] com communication channel associated to the USART
*/
static void ServeInterrupt(USART_TypeDef *u, FullDuplexDriver *com) {
uint16_t sr = u->SR;
if (sr & (SR_ORE | SR_FE | SR_PE | SR_LBD))
SetError(sr, com);
if (sr & SR_RXNE) {
chSysLockFromIsr();
chFDDIncomingDataI(com, u->DR);
chSysUnlockFromIsr();
}
if (sr & SR_TXE) {
chSysLockFromIsr();
msg_t b = chFDDRequestDataI(com);
chSysUnlockFromIsr();
if (b < Q_OK)
u->CR1 &= ~CR1_TXEIE;
else
u->DR = b;
}
}
#if USE_STM32_USART1 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorD4) {
CH_IRQ_PROLOGUE();
ServeInterrupt(USART1, &COM1);
CH_IRQ_EPILOGUE();
}
static void OutNotify1(void) {
USART1->CR1 |= CR1_TXEIE;
}
#endif
#if USE_STM32_USART2 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorD8) {
CH_IRQ_PROLOGUE();
ServeInterrupt(USART2, &COM2);
CH_IRQ_EPILOGUE();
}
static void OutNotify2(void) {
USART2->CR1 |= CR1_TXEIE;
}
#endif
#if USE_STM32_USART3 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorDC) {
CH_IRQ_PROLOGUE();
ServeInterrupt(USART3, &COM3);
CH_IRQ_EPILOGUE();
}
static void OutNotify3(void) {
USART3->CR1 |= CR1_TXEIE;
}
#endif
/**
* @brief USART1 setup.
* @details This function must be invoked with interrupts disabled.
* @param[in] u pointer to an USART I/O block
* @param[in] speed serial port speed in bits per second
* @param[in] cr1 the value for the @p CR1 register
* @param[in] cr2 the value for the @p CR2 register
* @param[in] cr3 the value for the @p CR3 register
* @note Must be invoked with interrupts disabled.
* @note Does not reset the I/O queues.
*/
void stm32_set_usart(USART_TypeDef *u, uint32_t speed, uint16_t cr1,
uint16_t cr2, uint16_t cr3) {
/*
* Baud rate setting.
*/
if (u == USART1)
u->BRR = APB2CLK / speed;
else
u->BRR = APB1CLK / speed;
/*
* Note that some bits are enforced.
*/
u->CR1 = cr1 | CR1_UE | CR1_PEIE | CR1_RXNEIE | CR1_TE | CR1_RE;
u->CR2 = cr2;
u->CR3 = cr3 | CR3_EIE;
}
/**
* @brief Serial driver initialization.
* @param[in] prio1 priority to be assigned to the USART1 IRQ
* @param[in] prio2 priority to be assigned to the USART2 IRQ
* @param[in] prio3 priority to be assigned to the USART3 IRQ
* @note Handshake pads are not enabled inside this function because they
* may have another use, enable them externally if needed.
* RX and TX pads are handled inside.
*/
void stm32_serial_init(uint32_t prio1, uint32_t prio2, uint32_t prio3) {
#if USE_STM32_USART1
chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
RCC->APB2ENR |= 0x00004000;
stm32_set_usart(USART1, STM32_USART_BITRATE, 0,
CR2_STOP1_BITS | CR2_LINEN, 0);
GPIOA->CRH = (GPIOA->CRH & 0xFFFFF00F) | 0x000004B0;
NVICEnableVector(USART1_IRQChannel, prio1);
#endif
#if USE_STM32_USART2
chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
RCC->APB1ENR |= 0x00020000;
stm32_set_usart(USART2, STM32_USART_BITRATE, 0,
CR2_STOP1_BITS | CR2_LINEN, 0);
GPIOA->CRL = (GPIOA->CRL & 0xFFFF00FF) | 0x00004B00;
NVICEnableVector(USART2_IRQChannel, prio2);
#endif
#if USE_STM32_USART3
chFDDInit(&COM3, ib3, sizeof ib3, NULL, ob3, sizeof ob3, OutNotify3);
RCC->APB1ENR |= 0x00040000;
stm32_set_usart(USART3, STM32_USART_BITRATE, 0,
CR2_STOP1_BITS | CR2_LINEN, 0);
GPIOB->CRH = (GPIOB->CRH & 0xFFFF00FF) | 0x00004B00;
NVICEnableVector(USART3_IRQChannel, prio3);
#endif
}
/** @} */
|
