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STM32 DMAv1 driver.
Driver capability:
- The driver supports the STM32 traditional DMA controller in the following
configurations: 5ch, 7ch, 7ch+5ch.
- Support for automatic the channel selection through the CSELR register.
- For devices without CSELR register it is possible to select channels but
the SYSCFG CFGR register is not configured, the user has to configure it
before starting the DMA driver.
- The driver supports shared ISR handlers with a quirk: the IRQ priority is
established by the first allocated channel among the channels sharing the
ISR.
The file registry must export:
STM32_ADVANCED_DMA - TRUE if CSELR is present.
STM32_DMAn_NUM_CHANNELS - Number of channels in DMA1.
STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x".
STM32_DMAn_CHxyz_HANDLER - Vector name for shared IRQs "x", "y" and "z".
STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x".
STM32_DMAn_CHxyz_NUMBER - Vector number for shared IRQs "x", "y" and "z".
Currently supported shared combinations are:
STM32_DMA1_CH23_HANDLER
STM32_DMA1_CH23_NUMBER
STM32_DMA1_CH4567_HANDLER
STM32_DMA1_CH4567_NUMBER
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