1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
|
/*
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SPC564Axx/boot.s
* @brief SPC564Axx boot-related code.
*
* @addtogroup PPC_BOOT
* @{
*/
#include "boot.h"
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .boot, "ax"
#if BOOT_USE_VLE
.long 0x015A0000
#else
.long 0x005A0000
#endif
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
#if BOOT_PERFORM_CORE_INIT
bl _coreinit
#endif
bl _ivinit
#if BOOT_RELOCATE_IN_RAM
/*
* Image relocation in RAM.
*/
lis %r4, __ram_reloc_start__@h
ori %r4, %r4, __ram_reloc_start__@l
lis %r5, __ram_reloc_dest__@h
ori %r5, %r5, __ram_reloc_dest__@l
lis %r6, __ram_reloc_end__@h
ori %r6, %r6, __ram_reloc_end__@l
.relloop:
cmpl cr0, %r4, %r6
bge cr0, .relend
lwz %r7, 0(%r4)
addi %r4, %r4, 4
stw %r7, 0(%r5)
addi %r5, %r5, 4
b .relloop
.relend:
lis %r3, _boot_address@h
ori %r3, %r3, _boot_address@l
mtctr %r3
bctrl
#else
b _boot_address
#endif
#if BOOT_PERFORM_CORE_INIT
.align 2
_ramcode:
tlbwe
isync
blr
.align 2
_coreinit:
/*
* Invalidating all TLBs except TLB1.
*/
lis %r3, 0
mtspr 625, %r3 /* MAS1 */
mtspr 626, %r3 /* MAS2 */
mtspr 627, %r3 /* MAS3 */
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
/*
* TLB0 allocated to internal RAM.
*/
lis %r3, TLB0_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB0_MAS1@h
ori %r3, %r3, TLB0_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB0_MAS2@h
ori %r3, %r3, TLB0_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB0_MAS3@h
ori %r3, %r3, TLB0_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB2 allocated to internal Peripherals Bridge A.
*/
lis %r3, TLB2_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB2_MAS1@h
ori %r3, %r3, TLB2_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB2_MAS2@h
ori %r3, %r3, TLB2_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB2_MAS3@h
ori %r3, %r3, TLB2_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB3 allocated to internal Peripherals Bridge B.
*/
lis %r3, TLB3_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB3_MAS1@h
ori %r3, %r3, TLB3_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB3_MAS2@h
ori %r3, %r3, TLB3_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB3_MAS3@h
ori %r3, %r3, TLB3_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB4 allocated to on-platform peripherals.
*/
lis %r3, TLB4_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB4_MAS1@h
ori %r3, %r3, TLB4_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB4_MAS2@h
ori %r3, %r3, TLB4_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB4_MAS3@h
ori %r3, %r3, TLB4_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor %r0, %r0, %r0
xor %r1, %r1, %r1
xor %r2, %r2, %r2
xor %r3, %r3, %r3
xor %r4, %r4, %r4
xor %r5, %r5, %r5
xor %r6, %r6, %r6
xor %r7, %r7, %r7
xor %r8, %r8, %r8
xor %r9, %r9, %r9
xor %r10, %r10, %r10
xor %r11, %r11, %r11
xor %r12, %r12, %r12
xor %r13, %r13, %r13
xor %r14, %r14, %r14
xor %r15, %r15, %r15
xor %r16, %r16, %r16
xor %r17, %r17, %r17
xor %r18, %r18, %r18
xor %r19, %r19, %r19
xor %r20, %r20, %r20
xor %r21, %r21, %r21
xor %r22, %r22, %r22
xor %r23, %r23, %r23
xor %r24, %r24, %r24
xor %r25, %r25, %r25
xor %r26, %r26, %r26
xor %r27, %r27, %r27
xor %r28, %r28, %r28
xor %r29, %r29, %r29
xor %r30, %r30, %r30
xor %r31, %r31, %r31
lis %r4, __ram_start__@h
ori %r4, %r4, __ram_start__@l
lis %r5, __ram_end__@h
ori %r5, %r5, __ram_end__@l
.cleareccloop:
cmpl %cr0, %r4, %r5
bge %cr0, .cleareccend
stmw %r16, 0(%r4)
addi %r4, %r4, 64
b .cleareccloop
.cleareccend:
/*
* *Finally* the TLB1 is re-allocated to flash, note, the final phase
* is executed from RAM.
*/
lis %r3, TLB1_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB1_MAS1@h
ori %r3, %r3, TLB1_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB1_MAS2@h
ori %r3, %r3, TLB1_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB1_MAS3@h
ori %r3, %r3, TLB1_MAS3@l
mtspr 627, %r3 /* MAS3 */
mflr %r4
lis %r6, _ramcode@h
ori %r6, %r6, _ramcode@l
lis %r7, 0x40010000@h
mtctr %r7
lwz %r3, 0(%r6)
stw %r3, 0(%r7)
lwz %r3, 4(%r6)
stw %r3, 4(%r7)
lwz %r3, 8(%r6)
stw %r3, 8(%r7)
bctrl
mtlr %r4
/*
* Branch prediction enabled.
*/
li %r3, BOOT_BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
/*
* Cache invalidated and then enabled.
*/
li %r3, LICSR1_ICINV
mtspr 1011, %r3 /* LICSR1 */
.inv: mfspr %r3, 1011 /* LICSR1 */
andi. %r3, %r3, LICSR1_ICINV
bne .inv
lis %r3, BOOT_LICSR1_DEFAULT@h
ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
mtspr 1011, %r3 /* LICSR1 */
blr
#endif /* BOOT_PERFORM_CORE_INIT */
/*
* Exception vectors initialization.
*/
.align 2
_ivinit:
/* MSR initialization.*/
lis %r3, BOOT_MSR_DEFAULT@h
ori %r3, %r3, BOOT_MSR_DEFAULT@l
mtMSR %r3
/* IVPR initialization.*/
lis %r3, __ivpr_base__@h
ori %r3, %r3, __ivpr_base__@l
mtIVPR %r3
/* IVORs initialization.*/
lis %r3, _unhandled_exception@h
ori %r3, %r3, _unhandled_exception@l
mtspr 400, %r3 /* IVOR0-15 */
mtspr 401, %r3
mtspr 402, %r3
mtspr 403, %r3
mtspr 404, %r3
mtspr 405, %r3
mtspr 406, %r3
mtspr 407, %r3
mtspr 408, %r3
mtspr 409, %r3
mtspr 410, %r3
mtspr 411, %r3
mtspr 412, %r3
mtspr 413, %r3
mtspr 414, %r3
mtspr 415, %r3
mtspr 528, %r3 /* IVOR32-34 */
mtspr 529, %r3
mtspr 530, %r3
blr
.section .handlers, "ax"
/*
* Unhandled exceptions handler.
*/
.weak _unhandled_exception
.type _unhandled_exception, @function
_unhandled_exception:
b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
