1 files changed, 27 insertions, 27 deletions

diff --git a/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
index 18e3d2f64..15c7fbcc7 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
@@ -139,7 +139,7 @@
  */

 #define STM32_ADC_COMPACT_SAMPLES           ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}

 #define STM32_ADC_USE_ADC1                  ${doc.STM32_ADC_USE_ADC1!"FALSE"}

-#define STM32_ADC_ADC1_DMA_CHANNEL          ${doc.STM32_ADC_ADC1_DMA_CHANNEL!"10"}

+#define STM32_ADC_ADC1_DMA_STREAM           ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

 #define STM32_ADC_ADC1_DMA_PRIORITY         ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}

 #define STM32_ADC_ADC12_IRQ_PRIORITY        ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}

 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}

@@ -161,8 +161,8 @@
 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}

 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}

 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}

-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL      ${doc.STM32_DAC_DAC1_CH1_DMA_CHANNEL!"11"}

-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL      ${doc.STM32_DAC_DAC1_CH2_DMA_CHANNEL!"12"}

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

 

 /*

  * GPT driver system settings.

@@ -191,12 +191,12 @@
 #define STM32_I2C_USE_I2C2                  ${doc.STM32_I2C_USE_I2C2!"FALSE"}

 #define STM32_I2C_USE_I2C3                  ${doc.STM32_I2C_USE_I2C3!"FALSE"}

 #define STM32_I2C_BUSY_TIMEOUT              ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}

-#define STM32_I2C_I2C1_RX_DMA_CHANNEL       ${doc.STM32_I2C_I2C1_RX_DMA_CHANNEL!"6"}

-#define STM32_I2C_I2C1_TX_DMA_CHANNEL       ${doc.STM32_I2C_I2C1_TX_DMA_CHANNEL!"7"}

-#define STM32_I2C_I2C2_RX_DMA_CHANNEL       ${doc.STM32_I2C_I2C2_RX_DMA_CHANNEL!"8"}

-#define STM32_I2C_I2C2_TX_DMA_CHANNEL       ${doc.STM32_I2C_I2C2_TX_DMA_CHANNEL!"9"}

-#define STM32_I2C_I2C3_RX_DMA_CHANNEL       ${doc.STM32_I2C_I2C3_RX_DMA_CHANNEL!"8"}

-#define STM32_I2C_I2C3_TX_DMA_CHANNEL       ${doc.STM32_I2C_I2C3_TX_DMA_CHANNEL!"9"}

+#define STM32_I2C_I2C1_RX_DMA_STREAM        ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_I2C_I2C1_TX_DMA_STREAM        ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_I2C_I2C2_RX_DMA_STREAM        ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_I2C_I2C2_TX_DMA_STREAM        ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_I2C_I2C3_RX_DMA_STREAM        ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_I2C_I2C3_TX_DMA_STREAM        ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

 #define STM32_I2C_I2C1_IRQ_PRIORITY         ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}

 #define STM32_I2C_I2C2_IRQ_PRIORITY         ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}

 #define STM32_I2C_I2C3_IRQ_PRIORITY         ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}

@@ -272,12 +272,12 @@
 #define STM32_SPI_USE_SPI1                  ${doc.STM32_SPI_USE_SPI1!"FALSE"}

 #define STM32_SPI_USE_SPI2                  ${doc.STM32_SPI_USE_SPI2!"FALSE"}

 #define STM32_SPI_USE_SPI3                  ${doc.STM32_SPI_USE_SPI3!"FALSE"}

-#define STM32_SPI_SPI1_RX_DMA_CHANNEL       ${doc.STM32_SPI_SPI1_RX_DMA_CHANNEL!"0"}

-#define STM32_SPI_SPI1_TX_DMA_CHANNEL       ${doc.STM32_SPI_SPI1_TX_DMA_CHANNEL!"1"}

-#define STM32_SPI_SPI2_RX_DMA_CHANNEL       ${doc.STM32_SPI_SPI2_RX_DMA_CHANNEL!"2"}

-#define STM32_SPI_SPI2_TX_DMA_CHANNEL       ${doc.STM32_SPI_SPI2_TX_DMA_CHANNEL!"3"}

-#define STM32_SPI_SPI3_RX_DMA_CHANNEL       ${doc.STM32_SPI_SPI3_RX_DMA_CHANNEL!"4"}

-#define STM32_SPI_SPI3_TX_DMA_CHANNEL       ${doc.STM32_SPI_SPI3_TX_DMA_CHANNEL!"5"}

+#define STM32_SPI_SPI1_RX_DMA_STREAM        ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_SPI_SPI1_TX_DMA_STREAM        ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_SPI_SPI2_RX_DMA_STREAM        ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_SPI_SPI2_TX_DMA_STREAM        ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_SPI_SPI3_RX_DMA_STREAM        ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_SPI_SPI3_TX_DMA_STREAM        ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

 #define STM32_SPI_SPI1_DMA_PRIORITY         ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}

 #define STM32_SPI_SPI2_DMA_PRIORITY         ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}

 #define STM32_SPI_SPI3_DMA_PRIORITY         ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}

@@ -305,16 +305,16 @@
 #define STM32_UART_USE_USART3               ${doc.STM32_UART_USE_USART3!"FALSE"}

 #define STM32_UART_USE_UART4                ${doc.STM32_UART_USE_UART4!"FALSE"}

 #define STM32_UART_USE_UART5                ${doc.STM32_UART_USE_UART5!"FALSE"}

-#define STM32_UART_USART1_RX_DMA_CHANNEL    ${doc.STM32_UART_USART1_RX_DMA_CHANNEL!"13"}

-#define STM32_UART_USART1_TX_DMA_CHANNEL    ${doc.STM32_UART_USART1_TX_DMA_CHANNEL!"0"}

-#define STM32_UART_USART2_RX_DMA_CHANNEL    ${doc.STM32_UART_USART2_RX_DMA_CHANNEL!"1"}

-#define STM32_UART_USART2_TX_DMA_CHANNEL    ${doc.STM32_UART_USART2_TX_DMA_CHANNEL!"2"}

-#define STM32_UART_USART3_RX_DMA_CHANNEL    ${doc.STM32_UART_USART3_RX_DMA_CHANNEL!"3"}

-#define STM32_UART_USART3_TX_DMA_CHANNEL    ${doc.STM32_UART_USART3_TX_DMA_CHANNEL!"4"}

-#define STM32_UART_UART4_RX_DMA_CHANNEL     ${doc.STM32_UART_UART4_RX_DMA_CHANNEL!"5"}

-#define STM32_UART_UART4_TX_DMA_CHANNEL     ${doc.STM32_UART_UART4_TX_DMA_CHANNEL!"6"}

-#define STM32_UART_UART5_RX_DMA_CHANNEL     ${doc.STM32_UART_UART5_RX_DMA_CHANNEL!"7"}

-#define STM32_UART_UART5_TX_DMA_CHANNEL     ${doc.STM32_UART_UART5_TX_DMA_CHANNEL!"8"}

+#define STM32_UART_USART1_RX_DMA_STREAM     ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_USART1_TX_DMA_STREAM     ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_USART2_RX_DMA_STREAM     ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_USART2_TX_DMA_STREAM     ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_USART3_RX_DMA_STREAM     ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_USART3_TX_DMA_STREAM     ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_UART4_RX_DMA_STREAM      ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_UART4_TX_DMA_STREAM      ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_UART5_RX_DMA_STREAM      ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_UART_UART5_TX_DMA_STREAM      ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

 #define STM32_UART_USART1_IRQ_PRIORITY      ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}

 #define STM32_UART_USART2_IRQ_PRIORITY      ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}

 #define STM32_UART_USART3_IRQ_PRIORITY      ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}

@@ -348,8 +348,8 @@
 #define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE ${doc.STM32_WSPI_OCTOSPI2_PRESCALER_VALUE!"1"}

 #define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    ${doc.STM32_WSPI_OCTOSPI1_IRQ_PRIORITY!"10"}

 #define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    ${doc.STM32_WSPI_OCTOSPI2_IRQ_PRIORITY!"10"}

-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     ${doc.STM32_WSPI_OCTOSPI1_DMA_CHANNEL!"9"}

-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     ${doc.STM32_WSPI_OCTOSPI2_DMA_CHANNEL!"10"}

+#define STM32_WSPI_OCTOSPI1_DMA_STREAM      ${doc.STM32_WSPI_OCTOSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

+#define STM32_WSPI_OCTOSPI2_DMA_STREAM      ${doc.STM32_WSPI_OCTOSPI2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}

 #define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    ${doc.STM32_WSPI_OCTOSPI1_DMA_PRIORITY!"1"}

 #define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    ${doc.STM32_WSPI_OCTOSPI2_DMA_PRIORITY!"1"}

 #define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY!"10"}