diff options
Diffstat (limited to 'testhal/STM32L1xx/SPI/main.c')
| -rw-r--r-- | testhal/STM32L1xx/SPI/main.c | 141 |
1 files changed, 141 insertions, 0 deletions
diff --git a/testhal/STM32L1xx/SPI/main.c b/testhal/STM32L1xx/SPI/main.c new file mode 100644 index 000000000..7a96f0e22 --- /dev/null +++ b/testhal/STM32L1xx/SPI/main.c @@ -0,0 +1,141 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * Maximum speed SPI configuration (16MHz, CPHA=0, CPOL=0, MSb first).
+ */
+static const SPIConfig hs_spicfg = {
+ NULL,
+ GPIOB,
+ 12,
+ 0
+};
+
+/*
+ * Low speed SPI configuration (256KHz, CPHA=0, CPOL=0, MSb first).
+ */
+static const SPIConfig ls_spicfg = {
+ NULL,
+ GPIOB,
+ 12,
+ SPI_CR1_BR_2 | SPI_CR1_BR_1
+};
+
+/*
+ * SPI TX and RX buffers.
+ */
+static uint8_t txbuf[512];
+static uint8_t rxbuf[512];
+
+/*
+ * SPI bus contender 1.
+ */
+static WORKING_AREA(spi_thread_1_wa, 256);
+static msg_t spi_thread_1(void *p) {
+
+ (void)p;
+ chRegSetThreadName("SPI thread 1");
+ while (TRUE) {
+ spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */
+ palClearPad(GPIOB, GPIOB_LED4); /* LED ON. */
+ spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */
+ spiSelect(&SPID2); /* Slave Select assertion. */
+ spiExchange(&SPID2, 512,
+ txbuf, rxbuf); /* Atomic transfer operations. */
+ spiUnselect(&SPID2); /* Slave Select de-assertion. */
+ spiReleaseBus(&SPID2); /* Ownership release. */
+ }
+ return 0;
+}
+
+/*
+ * SPI bus contender 2.
+ */
+static WORKING_AREA(spi_thread_2_wa, 256);
+static msg_t spi_thread_2(void *p) {
+
+ (void)p;
+ chRegSetThreadName("SPI thread 2");
+ while (TRUE) {
+ spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */
+ palSetPad(GPIOB, GPIOB_LED4); /* LED OFF. */
+ spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */
+ spiSelect(&SPID2); /* Slave Select assertion. */
+ spiExchange(&SPID2, 512,
+ txbuf, rxbuf); /* Atomic transfer operations. */
+ spiUnselect(&SPID2); /* Slave Select de-assertion. */
+ spiReleaseBus(&SPID2); /* Ownership release. */
+ }
+ return 0;
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ unsigned i;
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * SPI1 I/O pins setup.
+ */
+ palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL |
+ PAL_STM32_OSPEED_HIGHEST); /* NSS. */
+ palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) |
+ PAL_STM32_OSPEED_HIGHEST); /* SCK. */
+ palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */
+ palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) |
+ PAL_STM32_OSPEED_HIGHEST); /* MOSI. */
+ palSetPad(GPIOB, 12);
+
+ /*
+ * Prepare transmit pattern.
+ */
+ for (i = 0; i < sizeof(txbuf); i++)
+ txbuf[i] = (uint8_t)i;
+
+ /*
+ * Starting the transmitter and receiver threads.
+ */
+ chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa),
+ NORMALPRIO + 1, spi_thread_1, NULL);
+ chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa),
+ NORMALPRIO + 1, spi_thread_2, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+ return 0;
+}
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