diff options
Diffstat (limited to 'testhal/STM32F4xx/IRQ_STORM')
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/.cproject | 51 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/.project | 38 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/Makefile | 222 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/chconf.h | 533 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/halconf.h | 312 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/iar/ch.ewp | 2289 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/iar/ch.eww | 10 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/iar/ch.icf | 39 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/keil/ch.uvproj | 945 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/main.c | 327 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/mcuconf.h | 278 | ||||
-rw-r--r-- | testhal/STM32F4xx/IRQ_STORM/readme.txt | 31 |
12 files changed, 5075 insertions, 0 deletions
diff --git a/testhal/STM32F4xx/IRQ_STORM/.cproject b/testhal/STM32F4xx/IRQ_STORM/.cproject new file mode 100644 index 000000000..1e9c4518b --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/.cproject @@ -0,0 +1,51 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="0.415508998">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.415508998" moduleId="org.eclipse.cdt.core.settings" name="Default">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.415508998" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="0.415508998." name="/" resourcePath="">
+ <toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.80815107" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+ <targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.80815107.1895270004" name=""/>
+ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.728148619" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.libs.951102547" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.662656837" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1748846528" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1036788610" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.555497518" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1968480594" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1745911775" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="STM32F4xx-IRQ_STORM.null.256587885" name="STM32F4xx-IRQ_STORM"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="0.415508998">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>
diff --git a/testhal/STM32F4xx/IRQ_STORM/.project b/testhal/STM32F4xx/IRQ_STORM/.project new file mode 100644 index 000000000..6f3b0385f --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/.project @@ -0,0 +1,38 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>STM32F4xx-IRQ_STORM</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>board</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/boards/ST_STM32F4_DISCOVERY</locationURI>
+ </link>
+ <link>
+ <name>os</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/testhal/STM32F4xx/IRQ_STORM/Makefile b/testhal/STM32F4xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..86de6d81c --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/Makefile @@ -0,0 +1,222 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FWLIB),)
+ USE_FWLIB = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../..
+include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+include $(CHIBIOS)/test/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
+ifeq ($(USE_FWLIB),yes)
+ include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
+ CSRC += $(STM32SRC)
+ INCDIR += $(STM32INC)
+ USE_OPT += -DUSE_STDPERIPH_DRIVER
+endif
+
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk
diff --git a/testhal/STM32F4xx/IRQ_STORM/chconf.h b/testhal/STM32F4xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..38242d75d --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/chconf.h @@ -0,0 +1,533 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 20
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread automatically. The application has
+ * then the responsibility to do one of the following:
+ * - Spawn a custom idle thread at priority @p IDLEPRIO.
+ * - Change the main() thread priority to @p IDLEPRIO then enter
+ * an endless loop. In this scenario the @p main() thread acts as
+ * the idle thread.
+ * .
+ * @note Unless an idle thread is spawned the @p main() thread must not
+ * enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE FALSE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS FALSE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+#endif
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() { \
+ /* System tick event code here.*/ \
+}
+#endif
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#define CORTEX_USE_FPU FALSE
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32F4xx/IRQ_STORM/halconf.h b/testhal/STM32F4xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..117a5979b --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/halconf.h @@ -0,0 +1,312 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM TRUE
+#endif
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT TRUE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32F4xx/IRQ_STORM/iar/ch.ewp b/testhal/STM32F4xx/IRQ_STORM/iar/ch.ewp new file mode 100644 index 000000000..ffd2532c1 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/iar/ch.ewp @@ -0,0 +1,2289 @@ +<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>2</fileVersion>
+ <configuration>
+ <name>Debug</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>21</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>ExePath</name>
+ <state>Debug\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>Debug\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>Debug\List</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>19</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>3</version>
+ <state>6</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>2</version>
+ <state>7</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>5.10.0.159</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>STM32F4xxx ST STM32F4xxx</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave</name>
+ <version>19</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>19</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>0000000</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>$PROJ_DIR$\..\</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\kernel\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx\CMSIS\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\DMAv2</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\GPIOv2</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\SPIv1</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\USARTv1</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx</state>
+ <state>$PROJ_DIR$\..\..\..\..\boards\ST_STM32f4_DISCOVERY</state>
+ <state>$PROJ_DIR$\..\..\..\..\test</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IInterwork2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
+ </option>
+ <option>
+ <name>AIgnoreStdInclude</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AUserIncludes</name>
+ <state>$PROJ_DIR$\..</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx</state>
+ <state>$PROJ_DIR$\..\..\..\..\boards\ST_STM32f4_DISCOVERY</state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheckV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptionsV2</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>OBJCOPY</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>OOCOutputFormat</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCOutputOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OOCOutputFile</name>
+ <state>ch.srec</state>
+ </option>
+ <option>
+ <name>OOCCommandLineProducer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCObjCopyEnable</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>ILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>14</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>IlinkOutputFile</name>
+ <state>ch.out</state>
+ </option>
+ <option>
+ <name>IlinkLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkInputFileSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkDebugInfoEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkKeepSymbols</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkConfigDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkMapFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogInitialization</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogSection</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogVeneer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile</name>
+ <state>$PROJ_DIR$\ch.icf</state>
+ </option>
+ <option>
+ <name>IlinkIcfFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkSuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsRem</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkWarningsAreErrors</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkUseExtraOptions</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkLowLevelInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAutoLibEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAdditionalLibs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkOverrideProgramEntryLabel</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabel</name>
+ <state>__iar_program_start</state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>FillerStart</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>FillerEnd</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcInitialValue</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkBufferedTerminalOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkStdoutInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcFullSize</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIElfToolPostProcess</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogAutoLibSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogRedirSymbols</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogUnusedFragments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcReverseByteOrder</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcUseAsInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptInline</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsAllow</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsForce</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptMergeDuplSections</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptUseVfe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptForceVfe</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackAnalysisEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackControlFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkStackCallGraphFile</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARCHIVE</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>IarchiveInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IarchiveOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IarchiveOutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ </configuration>
+ <configuration>
+ <name>Release</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>0</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>21</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>ExePath</name>
+ <state>Release\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>Release\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>Release\List</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>19</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>3</version>
+ <state>6</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>2</version>
+ <state>7</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>5.10.0.159</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>STM32F4xxx ST STM32F4xxx</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave</name>
+ <version>19</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>19</version>
+ <state>38</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCDefines</name>
+ <state>NDEBUG</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>$PROJ_DIR$\..\</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\kernel\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx\CMSIS\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\include</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\DMAv2</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\GPIOv2</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\SPIv1</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\USARTv1</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx</state>
+ <state>$PROJ_DIR$\..\..\..\..\boards\ST_STM32f4_DISCOVERY</state>
+ <state>$PROJ_DIR$\..\..\..\..\test</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IInterwork2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>2</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
+ </option>
+ <option>
+ <name>AIgnoreStdInclude</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AUserIncludes</name>
+ <state>$PROJ_DIR$\..</state>
+ <state>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx</state>
+ <state>$PROJ_DIR$\..\..\..\..\boards\ST_STM32f4_DISCOVERY</state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheckV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptionsV2</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>OBJCOPY</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OOCOutputFormat</name>
+ <version>2</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCOutputOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OOCOutputFile</name>
+ <state>ch.hex</state>
+ </option>
+ <option>
+ <name>OOCCommandLineProducer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCObjCopyEnable</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>ILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>14</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IlinkOutputFile</name>
+ <state>ch.out</state>
+ </option>
+ <option>
+ <name>IlinkLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkInputFileSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkDebugInfoEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkKeepSymbols</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkConfigDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkMapFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogInitialization</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogModule</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogSection</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogVeneer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkIcfOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile</name>
+ <state>$PROJ_DIR$\ch.icf</state>
+ </option>
+ <option>
+ <name>IlinkIcfFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkSuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsRem</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkWarningsAreErrors</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkUseExtraOptions</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkLowLevelInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAutoLibEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAdditionalLibs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkOverrideProgramEntryLabel</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabel</name>
+ <state>__iar_program_start</state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>FillerStart</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>FillerEnd</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcInitialValue</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkBufferedTerminalOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkStdoutInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcFullSize</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIElfToolPostProcess</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogAutoLibSelect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogRedirSymbols</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogUnusedFragments</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkCrcReverseByteOrder</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcUseAsInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptInline</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsAllow</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsForce</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptMergeDuplSections</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptUseVfe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptForceVfe</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackAnalysisEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackControlFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkStackCallGraphFile</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARCHIVE</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IarchiveInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IarchiveOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IarchiveOutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ </configuration>
+ <group>
+ <name>board</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\boards\ST_STM32f4_DISCOVERY\board.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\boards\ST_STM32f4_DISCOVERY\board.h</name>
+ </file>
+ </group>
+ <group>
+ <name>os</name>
+ <group>
+ <name>hal</name>
+ <group>
+ <name>include</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\adc.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\can.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\ext.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\gpt.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\hal.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\i2c.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\icu.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\mac.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\mii.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\mmc_spi.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\pal.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\pwm.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\rtc.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\sdc.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\serial.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\serial_usb.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\spi.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\tm.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\uart.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\usb.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\include\usb_cdc.h</name>
+ </file>
+ </group>
+ <group>
+ <name>src</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\adc.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\can.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\ext.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\gpt.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\hal.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\i2c.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\icu.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\mac.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\mmc_spi.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\pal.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\pwm.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\rtc.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\sdc.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\serial.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\serial_usb.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\spi.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\tm.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\uart.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\src\usb.c</name>
+ </file>
+ </group>
+ </group>
+ <group>
+ <name>kernel</name>
+ <group>
+ <name>include</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\ch.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chcond.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chdebug.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chdynamic.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chevents.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chheap.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chinline.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chioch.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chlists.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chmboxes.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chmemcore.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chmempools.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chmsg.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chmtx.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chqueues.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chregistry.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chschd.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chsem.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chstreams.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chsys.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chthreads.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\include\chvt.h</name>
+ </file>
+ </group>
+ <group>
+ <name>src</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chcond.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chdebug.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chdynamic.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chevents.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chheap.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chlists.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chmboxes.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chmemcore.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chmempools.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chmsg.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chmtx.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chqueues.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chregistry.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chschd.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chsem.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chsys.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chthreads.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\kernel\src\chvt.c</name>
+ </file>
+ </group>
+ </group>
+ <group>
+ <name>platform</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\gpt_lld.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\gpt_lld.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\hal_lld.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\hal_lld.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32_dma.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32_dma.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\hal\platforms\STM32f4xx\stm32f4xx.h</name>
+ </file>
+ </group>
+ <group>
+ <name>port</name>
+ <group>
+ <name>STM32F4xx</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx\cmparams.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\STM32f4xx\vectors.s</name>
+ </file>
+ </group>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\chtypes.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\IAR\ARMCMx\cstartup.s</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx\nvic.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\os\ports\common\ARMCMx\nvic.h</name>
+ </file>
+ </group>
+ </group>
+ <group>
+ <name>test</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\test.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\test.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testbmk.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testbmk.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testdyn.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testdyn.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testevt.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testevt.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testheap.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testheap.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testmbox.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testmbox.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testmsg.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testmsg.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testmtx.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testmtx.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testpools.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testpools.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testqueues.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testqueues.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testsem.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testsem.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testthd.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\..\test\testthd.h</name>
+ </file>
+ </group>
+ <file>
+ <name>$PROJ_DIR$\..\chconf.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\halconf.h</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\main.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\mcuconf.h</name>
+ </file>
+</project>
+
+
diff --git a/testhal/STM32F4xx/IRQ_STORM/iar/ch.eww b/testhal/STM32F4xx/IRQ_STORM/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/iar/ch.eww @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\ch.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/testhal/STM32F4xx/IRQ_STORM/iar/ch.icf b/testhal/STM32F4xx/IRQ_STORM/iar/ch.icf new file mode 100644 index 000000000..c0a51f44c --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+/* Size of the IRQ Stack (Main Stack).*/
+define symbol __ICFEDIT_size_irqstack__ = 0x400;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK};
+define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {};
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {};
+define block SYSHEAP with alignment = 8 {section SYSHEAP};
+define block DATABSS with alignment = 8 {readwrite, zeroinit};
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section .intvec };
+
+place at address mem:__ICFEDIT_intvec_start__ {section .intvec};
+place in ROM_region {readonly};
+place at start of RAM_region {block IRQSTACK};
+place in RAM_region {block DATABSS, block HEAP};
+place in RAM_region {block SYSHEAP};
+place at end of RAM_region {block CSTACK};
diff --git a/testhal/STM32F4xx/IRQ_STORM/keil/ch.uvproj b/testhal/STM32F4xx/IRQ_STORM/keil/ch.uvproj new file mode 100644 index 000000000..b5e042b8a --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/keil/ch.uvproj @@ -0,0 +1,945 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd"> + + <SchemaVersion>1.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>Demo</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>STM32F407VG</Device> + <Vendor>STMicroelectronics</Vendor> + <Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile>"Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code")</StartupFile> + <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)</FlashDriverDll> + <DeviceId>6103</DeviceId> + <RegisterFile>stm32f4xx.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>SFD\ST\STM32F4xx\STM32F4xx.sfr</SFDFile> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath>ST\STM32F4xx\</RegisterFilePath> + <DBRegisterFilePath>ST\STM32F4xx\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\obj\</OutputDirectory> + <OutputName>ch</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\lst\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU</SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + <Simulator> + <UseSimulator>0</UseSimulator> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>1</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + </Simulator> + <Target> + <UseTarget>1</UseTarget> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>0</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>0</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + </Target> + <RunDebugAfterBuild>0</RunDebugAfterBuild> + <TargetSelection>8</TargetSelection> + <SimDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + </SimDlls> + <TargetDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + <Driver>STLink\ST-LINKIII-KEIL.dll</Driver> + </TargetDlls> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4100</DriverSelection> + </Flash1> + <Flash2>STLink\ST-LINKIII-KEIL.dll</Flash2> + <Flash3>"" ()</Flash3> + <Flash4></Flash4> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M4"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>2</RvdsVP> + <hadIRAM2>1</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>1</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x100000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x100000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x20020000</StartAddress> + <Size>0x1</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>4</Optim> + <oTime>1</oTime> + <SplitLS>0</SplitLS> + <OneElfS>0</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <VariousControls> + <MiscControls></MiscControls> + <Define>__heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base</Define> + <Undefine></Undefine> + <IncludePath>..\;..\..\..\..\os\kernel\include;..\..\..\..\os\ports\common\ARMCMx;..\..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\..\os\ports\RVCT\ARMCMx;..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx;..\..\..\..\os\hal\include;..\..\..\..\os\hal\platforms\STM32;..\..\..\..\os\hal\platforms\STM32\GPIOv2;..\..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\..\os\hal\platforms\STM32F4xx;..\..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\..\test</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <VariousControls> + <MiscControls>--cpreproc</MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath>..\;..\..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx</IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>1</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x08000000</TextAddressRange> + <DataAddressRange>0x20000000</DataAddressRange> + <ScatterFile></ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>board</GroupName> + <Files> + <File> + <FileName>board.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\boards\ST_STM32F4_DISCOVERY\board.c</FilePath> + </File> + <File> + <FileName>board.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\boards\ST_STM32F4_DISCOVERY\board.h</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>port</GroupName> + <Files> + <File> + <FileName>cstartup.s</FileName> + <FileType>2</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\cstartup.s</FilePath> + </File> + <File> + <FileName>chcoreasm_v7m.s</FileName> + <FileType>2</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s</FilePath> + </File> + <File> + <FileName>chcore.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\chcore.c</FilePath> + </File> + <File> + <FileName>chcore_v7m.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c</FilePath> + </File> + <File> + <FileName>chcore.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\chcore.h</FilePath> + </File> + <File> + <FileName>chcore_v7m.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h</FilePath> + </File> + <File> + <FileName>chtypes.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\chtypes.h</FilePath> + </File> + <File> + <FileName>cmparams.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\cmparams.h</FilePath> + </File> + <File> + <FileName>vectors.s</FileName> + <FileType>2</FileType> + <FilePath>..\..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\vectors.s</FilePath> + </File> + <File> + <FileName>nvic.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\ports\common\ARMCMx\nvic.c</FilePath> + </File> + <File> + <FileName>nvic.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\ports\common\ARMCMx\nvic.h</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>kernel</GroupName> + <Files> + <File> + <FileName>chcond.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chcond.c</FilePath> + </File> + <File> + <FileName>chdebug.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chdebug.c</FilePath> + </File> + <File> + <FileName>chdynamic.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chdynamic.c</FilePath> + </File> + <File> + <FileName>chevents.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chevents.c</FilePath> + </File> + <File> + <FileName>chheap.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chheap.c</FilePath> + </File> + <File> + <FileName>chlists.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chlists.c</FilePath> + </File> + <File> + <FileName>chmboxes.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chmboxes.c</FilePath> + </File> + <File> + <FileName>chmemcore.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chmemcore.c</FilePath> + </File> + <File> + <FileName>chmempools.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chmempools.c</FilePath> + </File> + <File> + <FileName>chmsg.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chmsg.c</FilePath> + </File> + <File> + <FileName>chmtx.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chmtx.c</FilePath> + </File> + <File> + <FileName>chqueues.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chqueues.c</FilePath> + </File> + <File> + <FileName>chregistry.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chregistry.c</FilePath> + </File> + <File> + <FileName>chschd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chschd.c</FilePath> + </File> + <File> + <FileName>chsem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chsem.c</FilePath> + </File> + <File> + <FileName>chsys.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chsys.c</FilePath> + </File> + <File> + <FileName>chthreads.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chthreads.c</FilePath> + </File> + <File> + <FileName>chvt.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\kernel\src\chvt.c</FilePath> + </File> + <File> + <FileName>ch.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\ch.h</FilePath> + </File> + <File> + <FileName>chbsem.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chbsem.h</FilePath> + </File> + <File> + <FileName>chcond.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chcond.h</FilePath> + </File> + <File> + <FileName>chdebug.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chdebug.h</FilePath> + </File> + <File> + <FileName>chdynamic.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chdynamic.h</FilePath> + </File> + <File> + <FileName>chevents.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chevents.h</FilePath> + </File> + <File> + <FileName>chfiles.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chfiles.h</FilePath> + </File> + <File> + <FileName>chheap.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chheap.h</FilePath> + </File> + <File> + <FileName>chinline.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chinline.h</FilePath> + </File> + <File> + <FileName>chioch.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chioch.h</FilePath> + </File> + <File> + <FileName>chlists.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chlists.h</FilePath> + </File> + <File> + <FileName>chmboxes.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chmboxes.h</FilePath> + </File> + <File> + <FileName>chmemcore.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chmemcore.h</FilePath> + </File> + <File> + <FileName>chmempools.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chmempools.h</FilePath> + </File> + <File> + <FileName>chmsg.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chmsg.h</FilePath> + </File> + <File> + <FileName>chmtx.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chmtx.h</FilePath> + </File> + <File> + <FileName>chqueues.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chqueues.h</FilePath> + </File> + <File> + <FileName>chregistry.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chregistry.h</FilePath> + </File> + <File> + <FileName>chschd.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chschd.h</FilePath> + </File> + <File> + <FileName>chsem.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chsem.h</FilePath> + </File> + <File> + <FileName>chstreams.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chstreams.h</FilePath> + </File> + <File> + <FileName>chsys.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chsys.h</FilePath> + </File> + <File> + <FileName>chthreads.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chthreads.h</FilePath> + </File> + <File> + <FileName>chvt.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\kernel\include\chvt.h</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>hal</GroupName> + <Files> + <File> + <FileName>hal.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\src\hal.c</FilePath> + </File> + <File> + <FileName>pal.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\src\pal.c</FilePath> + </File> + <File> + <FileName>serial.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\src\serial.c</FilePath> + </File> + <File> + <FileName>hal.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\include\hal.h</FilePath> + </File> + <File> + <FileName>pal.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\include\pal.h</FilePath> + </File> + <File> + <FileName>serial.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\include\serial.h</FilePath> + </File> + <File> + <FileName>gpt.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\include\gpt.h</FilePath> + </File> + <File> + <FileName>gpt.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\src\gpt.c</FilePath> + </File> + <File> + <FileName>tm.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\src\tm.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>platform</GroupName> + <Files> + <File> + <FileName>gpt_lld.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32\gpt_lld.h</FilePath> + </File> + <File> + <FileName>gpt_lld.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32\gpt_lld.c</FilePath> + </File> + <File> + <FileName>hal_lld.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c</FilePath> + </File> + <File> + <FileName>hal_lld.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h</FilePath> + </File> + <File> + <FileName>pal_lld.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c</FilePath> + </File> + <File> + <FileName>pal_lld.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h</FilePath> + </File> + <File> + <FileName>serial_lld.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c</FilePath> + </File> + <File> + <FileName>serial_lld.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h</FilePath> + </File> + <File> + <FileName>stm32_dma.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c</FilePath> + </File> + <File> + <FileName>stm32_dma.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h</FilePath> + </File> + <File> + <FileName>stm32_rcc.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h</FilePath> + </File> + <File> + <FileName>stm32l1xx.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\os\hal\platforms\STM32F4xx\stm32l1xx.h</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>test</GroupName> + <Files> + <File> + <FileName>test.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\test.c</FilePath> + </File> + <File> + <FileName>testbmk.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testbmk.c</FilePath> + </File> + <File> + <FileName>testdyn.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testdyn.c</FilePath> + </File> + <File> + <FileName>testevt.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testevt.c</FilePath> + </File> + <File> + <FileName>testheap.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testheap.c</FilePath> + </File> + <File> + <FileName>testmbox.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testmbox.c</FilePath> + </File> + <File> + <FileName>testmsg.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testmsg.c</FilePath> + </File> + <File> + <FileName>testmtx.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testmtx.c</FilePath> + </File> + <File> + <FileName>testpools.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testpools.c</FilePath> + </File> + <File> + <FileName>testqueues.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testqueues.c</FilePath> + </File> + <File> + <FileName>testsem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testsem.c</FilePath> + </File> + <File> + <FileName>testthd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\..\test\testthd.c</FilePath> + </File> + <File> + <FileName>test.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\test.h</FilePath> + </File> + <File> + <FileName>testbmk.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testbmk.h</FilePath> + </File> + <File> + <FileName>testdyn.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testdyn.h</FilePath> + </File> + <File> + <FileName>testevt.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testevt.h</FilePath> + </File> + <File> + <FileName>testheap.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testheap.h</FilePath> + </File> + <File> + <FileName>testmbox.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testmbox.h</FilePath> + </File> + <File> + <FileName>testmsg.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testmsg.h</FilePath> + </File> + <File> + <FileName>testmtx.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testmtx.h</FilePath> + </File> + <File> + <FileName>testpools.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testpools.h</FilePath> + </File> + <File> + <FileName>testqueues.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testqueues.h</FilePath> + </File> + <File> + <FileName>testsem.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testsem.h</FilePath> + </File> + <File> + <FileName>testthd.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\..\..\test\testthd.h</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>demo</GroupName> + <Files> + <File> + <FileName>main.c</FileName> + <FileType>1</FileType> + <FilePath>..\main.c</FilePath> + </File> + <File> + <FileName>mcuconf.h</FileName> + <FileType>5</FileType> + <FilePath>..\mcuconf.h</FilePath> + </File> + <File> + <FileName>chconf.h</FileName> + <FileType>5</FileType> + <FilePath>..\chconf.h</FilePath> + </File> + <File> + <FileName>halconf.h</FileName> + <FileType>5</FileType> + <FilePath>..\halconf.h</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + </Targets> + +</Project> diff --git a/testhal/STM32F4xx/IRQ_STORM/main.c b/testhal/STM32F4xx/IRQ_STORM/main.c new file mode 100644 index 000000000..905af44fe --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/main.c @@ -0,0 +1,327 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include <stdlib.h>
+
+#include "ch.h"
+#include "hal.h"
+
+/*===========================================================================*/
+/* Configurable settings. */
+/*===========================================================================*/
+
+#ifndef RANDOMIZE
+#define RANDOMIZE FALSE
+#endif
+
+#ifndef ITERATIONS
+#define ITERATIONS 100
+#endif
+
+#ifndef NUM_THREADS
+#define NUM_THREADS 4
+#endif
+
+#ifndef MAILBOX_SIZE
+#define MAILBOX_SIZE 4
+#endif
+
+/*===========================================================================*/
+/* Test related code. */
+/*===========================================================================*/
+
+#define MSG_SEND_LEFT 0
+#define MSG_SEND_RIGHT 1
+
+static bool_t saturated;
+
+/*
+ * Mailboxes and buffers.
+ */
+static Mailbox mb[NUM_THREADS];
+static msg_t b[NUM_THREADS][MAILBOX_SIZE];
+
+/*
+ * Test worker threads.
+ */
+static WORKING_AREA(waWorkerThread[NUM_THREADS], 128);
+static msg_t WorkerThread(void *arg) {
+ static volatile unsigned x = 0;
+ static unsigned cnt = 0;
+ unsigned me = (unsigned)arg;
+ unsigned target;
+ unsigned r;
+ msg_t msg;
+
+ chRegSetThreadName("worker");
+
+ /* Work loop.*/
+ while (TRUE) {
+ /* Waiting for a message.*/
+ chMBFetch(&mb[me], &msg, TIME_INFINITE);
+
+#if RANDOMIZE
+ /* Pseudo-random delay.*/
+ {
+ chSysLock();
+ r = rand() & 15;
+ chSysUnlock();
+ while (r--)
+ x++;
+ }
+#else
+ /* Fixed delay.*/
+ {
+ r = me >> 4;
+ while (r--)
+ x++;
+ }
+#endif
+
+ /* Deciding in which direction to re-send the message.*/
+ if (msg == MSG_SEND_LEFT)
+ target = me - 1;
+ else
+ target = me + 1;
+
+ if (target < NUM_THREADS) {
+ /* If this thread is not at the end of a chain re-sending the message,
+ note this check works because the variable target is unsigned.*/
+ msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE);
+ if (msg != RDY_OK)
+ saturated = TRUE;
+ }
+ else {
+ /* Provides a visual feedback about the system.*/
+ if (++cnt >= 500) {
+ cnt = 0;
+ palTogglePad(GPIOD, GPIOD_LED5);
+ }
+ }
+ }
+}
+
+/*
+ * GPT2 callback.
+ */
+static void gpt2cb(GPTDriver *gptp) {
+ msg_t msg;
+
+ (void)gptp;
+ chSysLockFromIsr();
+ msg = chMBPostI(&mb[0], MSG_SEND_RIGHT);
+ if (msg != RDY_OK)
+ saturated = TRUE;
+ chSysUnlockFromIsr();
+}
+
+/*
+ * GPT3 callback.
+ */
+static void gpt3cb(GPTDriver *gptp) {
+ msg_t msg;
+
+ (void)gptp;
+ chSysLockFromIsr();
+ msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT);
+ if (msg != RDY_OK)
+ saturated = TRUE;
+ chSysUnlockFromIsr();
+}
+
+/*
+ * GPT2 configuration.
+ */
+static const GPTConfig gpt2cfg = {
+ 1000000, /* 1MHz timer clock.*/
+ gpt2cb /* Timer callback.*/
+};
+
+/*
+ * GPT3 configuration.
+ */
+static const GPTConfig gpt3cfg = {
+ 1000000, /* 1MHz timer clock.*/
+ gpt3cb /* Timer callback.*/
+};
+
+
+/*===========================================================================*/
+/* Generic demo code. */
+/*===========================================================================*/
+
+static void print(char *p) {
+
+ while (*p) {
+ chSequentialStreamPut(&SD2, *p++);
+ }
+}
+
+static void println(char *p) {
+
+ while (*p) {
+ chSequentialStreamPut(&SD2, *p++);
+ }
+ chSequentialStreamWrite(&SD2, (uint8_t *)"\r\n", 2);
+}
+
+static void printn(uint32_t n) {
+ char buf[16], *p;
+
+ if (!n)
+ chSequentialStreamPut(&SD2, '0');
+ else {
+ p = buf;
+ while (n)
+ *p++ = (n % 10) + '0', n /= 10;
+ while (p > buf)
+ chSequentialStreamPut(&SD2, *--p);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ unsigned i;
+ gptcnt_t interval, threshold, worst;
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Prepares the Serial driver 2 and GPT drivers 2 and 3.
+ */
+ sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/
+ palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7));
+ palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7));
+ gptStart(&GPTD2, &gpt2cfg);
+ gptStart(&GPTD3, &gpt3cfg);
+
+ /*
+ * Initializes the mailboxes and creates the worker threads.
+ */
+ for (i = 0; i < NUM_THREADS; i++) {
+ chMBInit(&mb[i], b[i], MAILBOX_SIZE);
+ chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i],
+ NORMALPRIO - 20, WorkerThread, (void *)i);
+ }
+
+ /*
+ * Test procedure.
+ */
+ println("");
+ println("*** ChibiOS/RT IRQ-STORM long duration test");
+ println("***");
+ print("*** Kernel: ");
+ println(CH_KERNEL_VERSION);
+ print("*** Compiled: ");
+ println(__DATE__ " - " __TIME__);
+#ifdef CH_COMPILER_NAME
+ print("*** Compiler: ");
+ println(CH_COMPILER_NAME);
+#endif
+ print("*** Architecture: ");
+ println(CH_ARCHITECTURE_NAME);
+#ifdef CH_CORE_VARIANT_NAME
+ print("*** Core Variant: ");
+ println(CH_CORE_VARIANT_NAME);
+#endif
+#ifdef CH_PORT_INFO
+ print("*** Port Info: ");
+ println(CH_PORT_INFO);
+#endif
+#ifdef PLATFORM_NAME
+ print("*** Platform: ");
+ println(PLATFORM_NAME);
+#endif
+#ifdef BOARD_NAME
+ print("*** Test Board: ");
+ println(BOARD_NAME);
+#endif
+ println("***");
+ print("*** System Clock: ");
+ printn(STM32_SYSCLK);
+ println("");
+ print("*** Iterations: ");
+ printn(ITERATIONS);
+ println("");
+ print("*** Randomize: ");
+ printn(RANDOMIZE);
+ println("");
+ print("*** Threads: ");
+ printn(NUM_THREADS);
+ println("");
+ print("*** Mailbox size: ");
+ printn(MAILBOX_SIZE);
+ println("");
+
+ println("");
+ worst = 0;
+ for (i = 1; i <= ITERATIONS; i++){
+ print("Iteration ");
+ printn(i);
+ println("");
+ saturated = FALSE;
+ threshold = 0;
+ for (interval = 2000; interval >= 10; interval -= interval / 10) {
+ gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/
+ gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/
+ chThdSleepMilliseconds(1000);
+ gptStopTimer(&GPTD2);
+ gptStopTimer(&GPTD3);
+ if (!saturated)
+ print(".");
+ else {
+ print("#");
+ if (threshold == 0)
+ threshold = interval;
+ }
+ }
+ /* Gives the worker threads a chance to empty the mailboxes before next
+ cycle.*/
+ chThdSleepMilliseconds(20);
+ println("");
+ print("Saturated at ");
+ printn(threshold);
+ println(" uS");
+ println("");
+ if (threshold > worst)
+ worst = threshold;
+ }
+ gptStopTimer(&GPTD2);
+ gptStopTimer(&GPTD3);
+
+ print("Worst case at ");
+ printn(worst);
+ println(" uS");
+ println("");
+ println("Test Complete");
+
+ /*
+ * Normal main() thread activity, nothing in this test.
+ */
+ while (TRUE) {
+ chThdSleepMilliseconds(5000);
+ }
+}
diff --git a/testhal/STM32F4xx/IRQ_STORM/mcuconf.h b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..dc10c0604 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,278 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_VOS STM32_VOS_HIGH
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 TRUE
+#define STM32_GPT_USE_TIM3 TRUE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 6
+#define STM32_GPT_TIM3_IRQ_PRIORITY 10
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+#define STM32_GPT_TIM12_IRQ_PRIORITY 7
+#define STM32_GPT_TIM14_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 TRUE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
diff --git a/testhal/STM32F4xx/IRQ_STORM/readme.txt b/testhal/STM32F4xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..2b9f076f5 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/readme.txt @@ -0,0 +1,31 @@ +*****************************************************************************
+** ChibiOS/RT HAL - IRQ_STORM stress test demo for STM32F4xx. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an STMicroelectronics STM32F4-Discovery board.
+
+** The Demo **
+
+The application demonstrates the use of the STM32F4xx GPT, PAL and Serial
+drivers in order to implement a system stress demo.
+
+** Board Setup **
+
+None.
+
+** Build Procedure **
+
+The demo has been tested using the free Codesourcery GCC-based toolchain
+and YAGARTO.
+Just modify the TRGT line in the makefile in order to use different GCC ports.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
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