diff options
Diffstat (limited to 'testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c')
| -rw-r--r-- | testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c | 48 |
1 files changed, 41 insertions, 7 deletions
diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c index 226f4ba11..2e16ae935 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c +++ b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c @@ -45,7 +45,8 @@ const GPTConfig portab_gptcfg1 = { };
const ADCConfig portab_adccfg1 = {
- .difsel = 0U
+ .difsel = 0U,
+ .calibration = 0U
};
void adccallback(ADCDriver *adcp);
@@ -56,17 +57,50 @@ void adccallback(ADCDriver *adcp); void adcerrorcallback(ADCDriver *adcp, adcerror_t err);
/*
- * ADC conversion group.
- * Mode: Continuous, 16 samples of 2 channels, HW triggered by
- * GPT4-TRGO.
- * Channels: VRef, PA0.
+ * ADC conversion group 1.
+ * Mode: One shot, 2 channels, SW triggered.
+ * Channels: IN0, IN5.
*/
const ADCConversionGroup portab_adcgrpcfg1 = {
- .circular = true,
+ .circular = false,
.num_channels = ADC_GRP1_NUM_CHANNELS,
+ .end_cb = NULL,
+ .error_cb = adcerrorcallback,
+ .cfgr = 0U,
+ .cfgr2 = 0U,
+ .ccr = 0U,
+ .pcsel = ADC_SELMASK_IN0 | ADC_SELMASK_IN5,
+ .ltr1 = 0x00000000U,
+ .htr1 = 0x03FFFFFFU,
+ .ltr2 = 0x00000000U,
+ .htr2 = 0x03FFFFFFU,
+ .ltr3 = 0x00000000U,
+ .htr3 = 0x03FFFFFFU,
+ .smpr = {
+ ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_384P5) |
+ ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_384P5),
+ 0U
+ },
+ .sqr = {
+ ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN5),
+ 0U,
+ 0U,
+ 0U
+ }
+};
+
+/*
+ * ADC conversion group 2.
+ * Mode: Continuous, 2 channels, HW triggered by GPT4-TRGO.
+ * Channels: IN0, IN5.
+ */
+const ADCConversionGroup portab_adcgrpcfg2 = {
+ .circular = true,
+ .num_channels = ADC_GRP2_NUM_CHANNELS,
.end_cb = adccallback,
.error_cb = adcerrorcallback,
- .cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(12),
+ .cfgr = ADC_CFGR_EXTEN_RISING |
+ ADC_CFGR_EXTSEL_SRC(12), /* TIM4_TRGO */
.cfgr2 = 0U,
.ccr = 0U,
.pcsel = ADC_SELMASK_IN0 | ADC_SELMASK_IN5,
|