diff options
Diffstat (limited to 'testhal/STM32/STM32F7xx/GPT-ADC/main.c')
| -rw-r--r-- | testhal/STM32/STM32F7xx/GPT-ADC/main.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/testhal/STM32/STM32F7xx/GPT-ADC/main.c b/testhal/STM32/STM32F7xx/GPT-ADC/main.c index 150a7d260..e3790371a 100644 --- a/testhal/STM32/STM32F7xx/GPT-ADC/main.c +++ b/testhal/STM32/STM32F7xx/GPT-ADC/main.c @@ -17,6 +17,10 @@ #include "ch.h"
#include "hal.h"
+/* TRUE means that DMA-accessible buffers are placed in a non-cached RAM
+ area and that no cache management is required.*/
+#define DMA_BUFFERS_COHERENCE TRUE
+
/*===========================================================================*/
/* GPT driver related. */
/*===========================================================================*/
@@ -38,12 +42,15 @@ static const GPTConfig gpt4cfg1 = { #define ADC_GRP1_NUM_CHANNELS 2
#define ADC_GRP1_BUF_DEPTH 64
+#if !DMA_BUFFERS_COHERENCE
/* Note, the buffer is aligned to a 32 bytes boundary because limitations
imposed by the data cache. Note, this is GNU specific, it must be
- handled differently for other compilers.*/
+ handled differently for other compilers.
+ Only required if the ADC buffer is placed in a cache-able area.*/
#if defined(__GNUC__)
__attribute__((aligned (32)))
#endif
+#endif
static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
/*
@@ -52,7 +59,7 @@ static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; size_t nx = 0, ny = 0;
static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
-#if 0
+#if !DMA_BUFFERS_COHERENCE
/* DMA buffer invalidation because data cache, only invalidating the
half buffer just filled.
Only required if the ADC buffer is placed in a cache-able area.*/
|