diff options
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c | 203 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.h | 118 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 5 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h | 14 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h | 14 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c | 106 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c | 150 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h | 22 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32H7xx/stm32_registry.h | 2 |
10 files changed, 368 insertions, 270 deletions
diff --git a/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c b/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c index b19f99ad2..fcb2fc192 100644 --- a/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c +++ b/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c @@ -40,7 +40,7 @@ /*===========================================================================*/
/**
- * @brief Mask of the BDMA streams in @p bdma_streams_mask.
+ * @brief Mask of the BDMA streams in @p bdma_allocated_mask.
*/
#define STM32_BDMA_STREAMS_MASK 0x000000FFU
@@ -85,11 +85,20 @@ static struct { /**
* @brief Mask of the allocated streams.
*/
- uint32_t streams_mask;
+ uint32_t allocated_mask;
/**
- * @brief BDMA IRQ redirectors.
+ * @brief DMA IRQ redirectors.
*/
- bdma_isr_redir_t isr_redir[STM32_BDMA_STREAMS];
+ struct {
+ /**
+ * @brief DMA callback function.
+ */
+ stm32_bdmaisr_t func;
+ /**
+ * @brief DMA callback parameter.
+ */
+ void *param;
+ } streams[STM32_BDMA_STREAMS];
} bdma;
/*===========================================================================*/
@@ -112,8 +121,8 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH0_HANDLER) { flags = (BDMA->ISR >> 0U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 0U;
- if (bdma.isr_redir[0].func)
- bdma.isr_redir[0].func(bdma.isr_redir[0].param, flags);
+ if (bdma.streams[0].func)
+ bdma.streams[0].func(bdma.streams[0].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -130,8 +139,8 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH1_HANDLER) { flags = (BDMA->ISR >> 4U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 4U;
- if (bdma.isr_redir[1].func)
- bdma.isr_redir[1].func(bdma.isr_redir[1].param, flags);
+ if (bdma.streams[1].func)
+ bdma.streams[1].func(bdma.streams[1].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -148,8 +157,8 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH2_HANDLER) { flags = (BDMA->ISR >> 8U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 8U;
- if (bdma.isr_redir[2].func)
- bdma.isr_redir[2].func(bdma.isr_redir[2].param, flags);
+ if (bdma.streams[2].func)
+ bdma.streams[2].func(bdma.streams[2].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -166,8 +175,8 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH3_HANDLER) { flags = (BDMA->ISR >> 12U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 12U;
- if (bdma.isr_redir[3].func)
- bdma.isr_redir[3].func(bdma.isr_redir[3].param, flags);
+ if (bdma.streams[3].func)
+ bdma.streams[3].func(bdma.streams[3].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -184,8 +193,8 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH4_HANDLER) { flags = (BDMA->ISR >> 16U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 16U;
- if (bdma.isr_redir[4].func)
- bdma.isr_redir[4].func(bdma.isr_redir[4].param, flags);
+ if (bdma.streams[4].func)
+ bdma.streams[4].func(bdma.streams[4].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -202,8 +211,8 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH5_HANDLER) { flags = (BDMA->ISR >> 20U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 20U;
- if (bdma.isr_redir[5].func)
- bdma.isr_redir[5].func(bdma.isr_redir[5].param, flags);
+ if (bdma.streams[5].func)
+ bdma.streams[5].func(bdma.streams[5].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -220,8 +229,8 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH6_HANDLER) { flags = (BDMA->ISR >> 24U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 24U;
- if (bdma.isr_redir[6].func)
- bdma.isr_redir[6].func(bdma.isr_redir[6].param, flags);
+ if (bdma.streams[6].func)
+ bdma.streams[6].func(bdma.streams[6].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -238,8 +247,8 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH7_HANDLER) { flags = (BDMA->ISR >> 28U) & STM32_BDMA_ISR_MASK;
BDMA->IFCR = flags << 28U;
- if (bdma.isr_redir[7].func)
- bdma.isr_redir[7].func(bdma.isr_redir[7].param, flags);
+ if (bdma.streams[7].func)
+ bdma.streams[7].func(bdma.streams[7].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -256,11 +265,11 @@ OSAL_IRQ_HANDLER(STM32_BDMA1_CH7_HANDLER) { void bdmaInit(void) {
unsigned i;
- bdma.streams_mask = 0U;
+ bdma.allocated_mask = 0U;
for (i = 0; i < STM32_BDMA_STREAMS; i++) {
_stm32_bdma_streams[i].channel->CCR = 0U;
- bdma.isr_redir[i].func = NULL;
- bdma.isr_redir[i].param = NULL;
+ bdma.streams[i].func = NULL;
+ bdma.streams[i].param = NULL;
}
BDMA->IFCR = 0xFFFFFFFFU;
}
@@ -274,69 +283,111 @@ void bdmaInit(void) { * @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
- * @post The stream must be freed using @p bdmaStreamRelease() before it can
+ * @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
- * @note This function can be invoked in both ISR or thread context.
*
- * @param[in] stp pointer to an @p stm32_bdma_stream_t structure
+ * @param[in] id numeric identifiers of a specific stream or:
+ * - @p STM32_BDMA_STREAM_ID_ANY for any stream.
+ * .
* @param[in] priority IRQ priority for the BDMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
- * @return The operation status.
- * @retval false no error, stream taken.
- * @retval true error, stream already taken.
+ * @return Pointer to the allocated @p stm32_bdma_stream_t
+ * structure.
+ * @retval NULL if a/the stream is not available.
*
- * @special
+ * @iclass
*/
-bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp,
- uint32_t priority,
- stm32_bdmaisr_t func,
- void *param) {
-
- osalDbgCheck(stp != NULL);
-
- /* Checks if the stream is already taken.*/
- if ((bdma.streams_mask & (1U << stp->selfindex)) != 0U)
- return true;
+const stm32_bdma_stream_t *bdmaStreamAllocI(uint32_t id,
+ uint32_t priority,
+ stm32_bdmaisr_t func,
+ void *param) {
+ uint32_t i, startid, endid;
- /* Installs the BDMA handler.*/
- bdma.isr_redir[stp->selfindex].func = func;
- bdma.isr_redir[stp->selfindex].param = param;
- bdma.streams_mask |= (1U << stp->selfindex);
+ osalDbgCheckClassI();
- /* Enabling BDMA clocks required by the current streams set.*/
- if ((bdma.streams_mask & STM32_BDMA_STREAMS_MASK) == 0U) {
- rccEnableBDMA1(true);
+ if (id < STM32_BDMA_STREAMS) {
+ startid = id;
+ endid = id;
+ }
+ else if (id == STM32_BDMA_STREAM_ID_ANY) {
+ startid = 0U;
+ endid = STM32_BDMA_STREAMS - 1U;
+ }
+ else {
+ osalDbgCheck(false);
}
- /* Putting the stream in a safe state.*/
- bdmaStreamDisable(stp);
- stp->channel->CCR = STM32_BDMA_CR_RESET_VALUE;
-
- /* Enables the associated IRQ vector if not already enabled and if a
- callback is defined.*/
- if (func != NULL) {
- nvicEnableVector(stp->vector, priority);
+ for (i = startid; i <= endid; i++) {
+ uint32_t mask = (1U << i);
+ if ((bdma.allocated_mask & mask) == 0U) {
+ const stm32_bdma_stream_t *stp = STM32_BDMA_STREAM(i);
+
+ /* Installs the DMA handler.*/
+ bdma.streams[i].func = func;
+ bdma.streams[i].param = param;
+ bdma.allocated_mask |= mask;
+
+ /* Enabling DMA clocks required by the current streams set.*/
+ if ((STM32_BDMA_STREAMS_MASK & mask) != 0U) {
+ rccEnableBDMA1(true);
+ }
+
+#if defined(rccEnableDMAMUX)
+ /* Enabling DMAMUX if present.*/
+ if (bdma.allocated_mask != 0U) {
+ rccEnableDMAMUX(true);
+ }
+#endif
+
+ /* Enables the associated IRQ vector if not already enabled and if a
+ callback is defined.*/
+ if (func != NULL) {
+ nvicEnableVector(stp->vector, priority);
+ }
+
+ /* Putting the stream in a known state.*/
+ bdmaStreamDisable(stp);
+ stp->channel->CCR = STM32_BDMA_CR_RESET_VALUE;
+
+ return stp;
+ }
}
- return false;
+ return NULL;
}
/**
- * @brief Associates a peripheral request to a BDMA stream.
+ * @brief Allocates a BDMA stream.
+ * @details The stream is allocated and, if required, the BDMA clock enabled.
+ * The function also enables the IRQ vector associated to the stream
+ * and initializes its priority.
+ * @pre The stream must not be already in use or an error is returned.
+ * @post The stream is allocated and the default ISR handler redirected
+ * to the specified function.
+ * @post The stream ISR vector is enabled and its priority configured.
+ * @post The stream must be freed using @p bdmaStreamRelease() before it can
+ * be reused with another peripheral.
+ * @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
- * @param[in] stp pointer to a @p stm32_bdma_stream_t structure
- * @param[in] per peripheral identifier
+ * @param[in] stp pointer to an @p stm32_bdma_stream_t structure
+ * @param[in] priority IRQ priority for the BDMA stream
+ * @param[in] func handling function pointer, can be @p NULL
+ * @param[in] param a parameter to be passed to the handling function
+ * @return The operation status.
+ * @retval false no error, stream taken.
+ * @retval true error, stream already taken.
*
* @special
*/
-void bdmaSetRequestSource(const stm32_bdma_stream_t *stp, uint32_t per) {
-
- osalDbgCheck(per < 256U);
+bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp,
+ uint32_t priority,
+ stm32_bdmaisr_t func,
+ void *param) {
- stp->mux->CCR = per;
+ return bdmaStreamAllocI(stp->selfindex, priority, func, param) == NULL;
}
/**
@@ -357,25 +408,41 @@ void bdmaStreamRelease(const stm32_bdma_stream_t *stp) { osalDbgCheck(stp != NULL);
/* Check if the streams is not taken.*/
- osalDbgAssert((bdma.streams_mask & (1U << stp->selfindex)) != 0U,
+ osalDbgAssert((bdma.allocated_mask & (1U << stp->selfindex)) != 0U,
"not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(stp->vector);
/* Marks the stream as not allocated.*/
- bdma.streams_mask &= ~(1U << stp->selfindex);
+ bdma.allocated_mask &= ~(1U << stp->selfindex);
/* Clearing associated handler and parameter.*/
- bdma.isr_redir->func = NULL;
- bdma.isr_redir->param = NULL;
+ bdma.streams->func = NULL;
+ bdma.streams->param = NULL;
/* Shutting down clocks that are no more required, if any.*/
- if ((bdma.streams_mask & STM32_BDMA_STREAMS_MASK) == 0U) {
+ if ((bdma.allocated_mask & STM32_BDMA_STREAMS_MASK) == 0U) {
rccDisableBDMA1();
}
}
+/**
+ * @brief Associates a peripheral request to a BDMA stream.
+ * @note This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] stp pointer to a @p stm32_bdma_stream_t structure
+ * @param[in] per peripheral identifier
+ *
+ * @special
+ */
+void bdmaSetRequestSource(const stm32_bdma_stream_t *stp, uint32_t per) {
+
+ osalDbgCheck(per < 256U);
+
+ stp->mux->CCR = per;
+}
+
#endif /* STM32_BDMA_REQUIRED */
/** @} */
diff --git a/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.h b/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.h index 1dcc090bc..337dcfcb9 100644 --- a/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.h +++ b/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.h @@ -35,12 +35,12 @@ * @brief Total number of BDMA streams.
* @details This is the total number of streams among all the BDMA units.
*/
-#define STM32_BDMA_STREAMS 8U
+#define STM32_BDMA_STREAMS 8U
/**
* @brief Mask of the ISR bits passed to the BDMA callback functions.
*/
-#define STM32_BDMA_ISR_MASK 0x0EU
+#define STM32_BDMA_ISR_MASK 0x0EU
/**
* @brief Checks if a BDMA priority is within the valid range.
@@ -50,7 +50,7 @@ * @retval false invalid BDMA priority.
* @retval true correct BDMA priority.
*/
-#define STM32_BDMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
+#define STM32_BDMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
/**
* @brief Checks if a BDMA channel is within the valid range.
@@ -60,7 +60,15 @@ * @retval FALSE invalid DMA channel.
* @retval TRUE correct DMA channel.
*/
-#define STM32_BDMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && ((ch) <= 7U))
+#define STM32_BDMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
+ ((ch) <= STM32_BDMA_STREAMS))
+
+/**
+ * @name Special stream identifiers
+ * @{
+ */
+#define STM32_BDMA_STREAM_ID_ANY STM32_BDMA_STREAMS
+/** @} */
/**
* @name BDMA streams identifiers
@@ -73,55 +81,55 @@ * @return A pointer to the stm32_bdma_stream_t constant structure
* associated to the BDMA stream.
*/
-#define STM32_BDMA_STREAM(id) (&_stm32_bdma_streams[id])
-
-#define STM32_BDMA1_STREAM0 STM32_BDMA_STREAM(0)
-#define STM32_BDMA1_STREAM1 STM32_BDMA_STREAM(1)
-#define STM32_BDMA1_STREAM2 STM32_BDMA_STREAM(2)
-#define STM32_BDMA1_STREAM3 STM32_BDMA_STREAM(3)
-#define STM32_BDMA1_STREAM4 STM32_BDMA_STREAM(4)
-#define STM32_BDMA1_STREAM5 STM32_BDMA_STREAM(5)
-#define STM32_BDMA1_STREAM6 STM32_BDMA_STREAM(6)
-#define STM32_BDMA1_STREAM7 STM32_BDMA_STREAM(7)
+#define STM32_BDMA_STREAM(id) (&_stm32_bdma_streams[id])
+
+#define STM32_BDMA1_STREAM0 STM32_BDMA_STREAM(0)
+#define STM32_BDMA1_STREAM1 STM32_BDMA_STREAM(1)
+#define STM32_BDMA1_STREAM2 STM32_BDMA_STREAM(2)
+#define STM32_BDMA1_STREAM3 STM32_BDMA_STREAM(3)
+#define STM32_BDMA1_STREAM4 STM32_BDMA_STREAM(4)
+#define STM32_BDMA1_STREAM5 STM32_BDMA_STREAM(5)
+#define STM32_BDMA1_STREAM6 STM32_BDMA_STREAM(6)
+#define STM32_BDMA1_STREAM7 STM32_BDMA_STREAM(7)
/** @} */
/**
* @name CR register constants
* @{
*/
-#define STM32_BDMA_CR_RESET_VALUE 0x00000000U
-#define STM32_BDMA_CR_EN BDMA_CCR_EN_Msk
-#define STM32_BDMA_CR_TCIE BDMA_CCR_TCIE
-#define STM32_BDMA_CR_HTIE BDMA_CCR_HTIE
-#define STM32_BDMA_CR_TEIE BDMA_CCR_TEIE
-#define STM32_BDMA_CR_DIR_MASK (BDMA_CCR_DIR | BDMA_CCR_MEM2MEM)
-#define STM32_BDMA_CR_DIR_P2M 0U
-#define STM32_BDMA_CR_DIR_M2P BDMA_CCR_DIR
-#define STM32_BDMA_CR_DIR_M2M BDMA_CCR_MEM2MEM
-#define STM32_BDMA_CR_CIRC BDMA_CCR_CIRC
-#define STM32_BDMA_CR_PINC BDMA_CCR_PINC
-#define STM32_BDMA_CR_MINC BDMA_CCR_MINC
-#define STM32_BDMA_CR_PSIZE_MASK BDMA_CCR_PSIZE_Msk
-#define STM32_BDMA_CR_PSIZE_BYTE 0U
-#define STM32_BDMA_CR_PSIZE_HWORD BDMA_CCR_PSIZE_0
-#define STM32_BDMA_CR_PSIZE_WORD BDMA_CCR_PSIZE_1
-#define STM32_BDMA_CR_MSIZE_MASK BDMA_CCR_MSIZE_Msk
-#define STM32_BDMA_CR_MSIZE_BYTE 0U
-#define STM32_BDMA_CR_MSIZE_HWORD BDMA_CCR_MSIZE_0
-#define STM32_BDMA_CR_MSIZE_WORD BDMA_CCR_MSIZE_1
-#define STM32_BDMA_CR_SIZE_MASK (STM32_BDMA_CR_PSIZE_MASK | \
- STM32_BDMA_CR_MSIZE_MASK)
-#define STM32_BDMA_CR_PL_MASK BDMA_CCR_PL_Msk
-#define STM32_BDMA_CR_PL(n) ((n) << 12U)
+#define STM32_BDMA_CR_RESET_VALUE 0x00000000U
+#define STM32_BDMA_CR_EN BDMA_CCR_EN_Msk
+#define STM32_BDMA_CR_TCIE BDMA_CCR_TCIE
+#define STM32_BDMA_CR_HTIE BDMA_CCR_HTIE
+#define STM32_BDMA_CR_TEIE BDMA_CCR_TEIE
+#define STM32_BDMA_CR_DIR_MASK (BDMA_CCR_DIR | BDMA_CCR_MEM2MEM)
+#define STM32_BDMA_CR_DIR_P2M 0U
+#define STM32_BDMA_CR_DIR_M2P BDMA_CCR_DIR
+#define STM32_BDMA_CR_DIR_M2M BDMA_CCR_MEM2MEM
+#define STM32_BDMA_CR_CIRC BDMA_CCR_CIRC
+#define STM32_BDMA_CR_PINC BDMA_CCR_PINC
+#define STM32_BDMA_CR_MINC BDMA_CCR_MINC
+#define STM32_BDMA_CR_PSIZE_MASK BDMA_CCR_PSIZE_Msk
+#define STM32_BDMA_CR_PSIZE_BYTE 0U
+#define STM32_BDMA_CR_PSIZE_HWORD BDMA_CCR_PSIZE_0
+#define STM32_BDMA_CR_PSIZE_WORD BDMA_CCR_PSIZE_1
+#define STM32_BDMA_CR_MSIZE_MASK BDMA_CCR_MSIZE_Msk
+#define STM32_BDMA_CR_MSIZE_BYTE 0U
+#define STM32_BDMA_CR_MSIZE_HWORD BDMA_CCR_MSIZE_0
+#define STM32_BDMA_CR_MSIZE_WORD BDMA_CCR_MSIZE_1
+#define STM32_BDMA_CR_SIZE_MASK (STM32_BDMA_CR_PSIZE_MASK | \
+ STM32_BDMA_CR_MSIZE_MASK)
+#define STM32_BDMA_CR_PL_MASK BDMA_CCR_PL_Msk
+#define STM32_BDMA_CR_PL(n) ((n) << 12U)
/** @} */
/**
* @name Status flags passed to the ISR callbacks
* @{
*/
-#define STM32_BDMA_ISR_TEIF BDMA_ISR_TEIF1
-#define STM32_BDMA_ISR_HTIF BDMA_ISR_HTIF1
-#define STM32_BDMA_ISR_TCIF BDMA_ISR_TCIF1
+#define STM32_BDMA_ISR_TEIF BDMA_ISR_TEIF1
+#define STM32_BDMA_ISR_HTIF BDMA_ISR_HTIF1
+#define STM32_BDMA_ISR_TCIF BDMA_ISR_TCIF1
/** @} */
/*===========================================================================*/
@@ -205,27 +213,27 @@ /*===========================================================================*/
/**
+ * @brief STM32 BDMA ISR function type.
+ *
+ * @param[in] p parameter for the registered function
+ * @param[in] flags pre-shifted content of the ISR register, the bits
+ * are aligned to bit zero
+ */
+typedef void (*stm32_bdmaisr_t)(void *p, uint32_t flags);
+
+/**
* @brief STM32 BDMA stream descriptor structure.
*/
typedef struct {
BDMA_TypeDef *bdma ; /**< @brief Associated BDMA. */
BDMA_Channel_TypeDef *channel; /**< @brief Associated BDMA channel.*/
- uint8_t ishift; /**< @brief Bit offset in ISR and
+ uint8_t shift; /**< @brief Bit offset in ISR and
IFCR registers. */
DMAMUX_Channel_TypeDef *mux; /**< @brief Associated BDMA stream. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
} stm32_bdma_stream_t;
-/**
- * @brief STM32 BDMA ISR function type.
- *
- * @param[in] p parameter for the registered function
- * @param[in] flags pre-shifted content of the ISR register, the bits
- * are aligned to bit zero
- */
-typedef void (*stm32_bdmaisr_t)(void *p, uint32_t flags);
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
@@ -352,7 +360,7 @@ typedef void (*stm32_bdmaisr_t)(void *p, uint32_t flags); * @special
*/
#define bdmaStreamClearInterrupt(stp) { \
- (stp)->bdma->IFCR = STM32_BDMA_ISR_MASK << (stp)->ishift; \
+ (stp)->bdma->IFCR = STM32_BDMA_ISR_MASK << (stp)->shift; \
}
/**
@@ -409,12 +417,16 @@ extern const stm32_bdma_stream_t _stm32_bdma_streams[STM32_BDMA_STREAMS]; extern "C" {
#endif
void bdmaInit(void);
+ const stm32_bdma_stream_t *bdmaStreamAllocI(uint32_t id,
+ uint32_t priority,
+ stm32_bdmaisr_t func,
+ void *param);
bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp,
uint32_t priority,
stm32_bdmaisr_t func,
void *param);
- void bdmaSetRequestSource(const stm32_bdma_stream_t *stp, uint32_t per);
void bdmaStreamRelease(const stm32_bdma_stream_t *stp);
+ void bdmaSetRequestSource(const stm32_bdma_stream_t *stp, uint32_t per);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c index f6ede4a6a..cabc8d5dc 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c @@ -540,6 +540,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, startid = id;
endid = id;
}
+#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
else if (id == STM32_DMA_STREAM_ID_ANY) {
startid = 0U;
endid = STM32_DMA_STREAMS - 1U;
@@ -554,6 +555,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, endid = STM32_DMA_STREAMS - 1U;
}
#endif
+#endif
else {
osalDbgCheck(false);
}
@@ -566,7 +568,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, /* Installs the DMA handler.*/
dma.streams[i].func = func;
dma.streams[i].param = param;
- dma.allocated_mask |= mask;
+ dma.allocated_mask |= mask;
/* Enabling DMA clocks required by the current streams set.*/
if ((STM32_DMA1_STREAMS_MASK & mask) != 0U) {
@@ -595,6 +597,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, }
/* Putting the stream in a known state.*/
+ dmaStreamDisable(dmastp);
dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
return dmastp;
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h index 3316f19f7..3bb5ff4ca 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h @@ -77,6 +77,7 @@ */
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
+#if (STM32_DMA_SUPPORTS_DMAMUX == FALSE) || defined(_DOXYGEN__)
/**
* @brief Checks if a DMA channel is within the valid range.
*
@@ -87,6 +88,15 @@ */
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) < STM32_DMA_STREAMS))
+#else /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
+#if STM32_DMA2_NUM_CHANNELS > 0
+#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
+ ((ch) <= (STM32_DMA_STREAMS + 2)))
+#else
+#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
+ ((ch) <= (STM32_DMA_STREAMS + 1)))
+#endif
+#endif /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
/**
* @brief Returns an unique numeric identifier for a DMA stream.
@@ -120,14 +130,18 @@ */
#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(_DOXYGEN__)
/**
* @name Special stream identifiers
* @{
*/
#define STM32_DMA_STREAM_ID_ANY STM32_DMA_STREAMS
#define STM32_DMA_STREAM_ID_ANY_DMA1 (STM32_DMA_STREAM_ID_ANY + 1)
+#if STM32_DMA2_NUM_CHANNELS > 0
#define STM32_DMA_STREAM_ID_ANY_DMA2 (STM32_DMA_STREAM_ID_ANY_DMA1 + 1)
+#endif
/** @} */
+#endif
/**
* @name DMA streams identifiers
diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c index c048036a8..1a214fb70 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c @@ -507,6 +507,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, startid = id;
endid = id;
}
+#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
else if (id == STM32_DMA_STREAM_ID_ANY) {
startid = 0U;
endid = STM32_DMA_STREAMS - 1U;
@@ -519,6 +520,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, startid = (STM32_DMA_STREAMS / 2U) - 1U;
endid = STM32_DMA_STREAMS - 1U;
}
+#endif
else {
osalDbgCheck(false);
}
@@ -531,7 +533,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, /* Installs the DMA handler.*/
dma.streams[i].func = func;
dma.streams[i].param = param;
- dma.allocated_mask |= mask;
+ dma.allocated_mask |= mask;
/* Enabling DMA clocks required by the current streams set.*/
if ((STM32_DMA1_STREAMS_MASK & mask) != 0U) {
diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h index d331709b6..8e298afe9 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h @@ -67,6 +67,7 @@ */
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
+#if (STM32_DMA_SUPPORTS_DMAMUX == FALSE) || defined(_DOXYGEN__)
/**
* @brief Checks if a DMA channel is within the valid range.
*
@@ -77,6 +78,15 @@ */
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
((ch) <= STM32_DMA_STREAMS))
+#else /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
+#if STM32_HAS_DMA2 == TRUE
+#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
+ ((ch) <= (STM32_DMA_STREAMS + 2)))
+#else
+#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
+ ((ch) <= (STM32_DMA_STREAMS + 1)))
+#endif
+#endif /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
/**
* @brief Returns an unique numeric identifier for a DMA stream.
@@ -109,14 +119,18 @@ */
#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(_DOXYGEN__)
/**
* @name Special stream identifiers
* @{
*/
#define STM32_DMA_STREAM_ID_ANY STM32_DMA_STREAMS
#define STM32_DMA_STREAM_ID_ANY_DMA1 (STM32_DMA_STREAM_ID_ANY + 1)
+#if STM32_HAS_DMA2 == TRUE
#define STM32_DMA_STREAM_ID_ANY_DMA2 (STM32_DMA_STREAM_ID_ANY_DMA1 + 1)
+#endif
/** @} */
+#endif
/**
* @name DMA streams identifiers
diff --git a/os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c index 3ddeca982..b1e8c38a2 100644 --- a/os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c +++ b/os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c @@ -701,8 +701,8 @@ void i2c_lld_init(void) { #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
I2CD1.is_bdma = false;
#endif
- I2CD1.rx.dma = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_CHANNEL);
- I2CD1.tx.dma = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_CHANNEL);
+ I2CD1.rx.dma = NULL;
+ I2CD1.tx.dma = NULL;
#endif
#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY);
@@ -722,8 +722,8 @@ void i2c_lld_init(void) { #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
I2CD2.is_bdma = false;
#endif
- I2CD2.rx.dma = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_CHANNEL);
- I2CD2.tx.dma = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_CHANNEL);
+ I2CD2.rx.dma = NULL;
+ I2CD2.tx.dma = NULL;
#endif
#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY);
@@ -743,8 +743,8 @@ void i2c_lld_init(void) { #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
I2CD3.is_bdma = false;
#endif
- I2CD3.rx.dma = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_CHANNEL);
- I2CD3.tx.dma = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_CHANNEL);
+ I2CD3.rx.dma = NULL;
+ I2CD3.tx.dma = NULL;
#endif
#if defined(STM32_I2C3_GLOBAL_NUMBER) || defined(__DOXYGEN__)
nvicEnableVector(STM32_I2C3_GLOBAL_NUMBER, STM32_I2C_I2C3_IRQ_PRIORITY);
@@ -762,10 +762,10 @@ void i2c_lld_init(void) { I2CD4.i2c = I2C4;
#if STM32_I2C_USE_DMA == TRUE
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
- I2CD1.is_bdma = true;
+ I2CD4.is_bdma = true;
#endif
- I2CD4.rx.bdma = STM32_BDMA_STREAM(STM32_I2C_I2C4_RX_BDMA_CHANNEL);
- I2CD4.tx.bdma = STM32_BDMA_STREAM(STM32_I2C_I2C4_TX_BDMA_CHANNEL);
+ I2CD4.rx.bdma = NULL;
+ I2CD4.tx.bdma = NULL;
#endif
#if defined(STM32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__)
nvicEnableVector(STM32_I2C4_GLOBAL_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY);
@@ -823,18 +823,16 @@ void i2c_lld_start(I2CDriver *i2cp) { rccEnableI2C1(true);
#if STM32_I2C_USE_DMA == TRUE
{
- bool b;
-
- b = dmaStreamAllocate(i2cp->rx.dma,
- STM32_I2C_I2C1_IRQ_PRIORITY,
- NULL,
- (void *)i2cp);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(i2cp->tx.dma,
- STM32_I2C_I2C1_IRQ_PRIORITY,
- NULL,
- (void *)i2cp);
- osalDbgAssert(!b, "stream already allocated");
+ i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C1_RX_DMA_CHANNEL,
+ STM32_I2C_I2C1_IRQ_PRIORITY,
+ NULL,
+ NULL);
+ osalDbgAssert(i2cp->rx.dma != NULL, "unable to allocate stream");
+ i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C1_TX_DMA_CHANNEL,
+ STM32_I2C_I2C1_IRQ_PRIORITY,
+ NULL,
+ NULL);
+ osalDbgAssert(i2cp->tx.dma != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
i2cp->txdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
@@ -852,18 +850,16 @@ void i2c_lld_start(I2CDriver *i2cp) { rccEnableI2C2(true);
#if STM32_I2C_USE_DMA == TRUE
{
- bool b;
-
- b = dmaStreamAllocate(i2cp->rx.dma,
- STM32_I2C_I2C2_IRQ_PRIORITY,
- NULL,
- (void *)i2cp);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(i2cp->tx.dma,
- STM32_I2C_I2C2_IRQ_PRIORITY,
- NULL,
- (void *)i2cp);
- osalDbgAssert(!b, "stream already allocated");
+ i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C2_RX_DMA_CHANNEL,
+ STM32_I2C_I2C2_IRQ_PRIORITY,
+ NULL,
+ NULL);
+ osalDbgAssert(i2cp->rx.dma != NULL, "unable to allocate stream");
+ i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C2_TX_DMA_CHANNEL,
+ STM32_I2C_I2C2_IRQ_PRIORITY,
+ NULL,
+ NULL);
+ osalDbgAssert(i2cp->tx.dma != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
i2cp->txdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
@@ -881,18 +877,16 @@ void i2c_lld_start(I2CDriver *i2cp) { rccEnableI2C3(true);
#if STM32_I2C_USE_DMA == TRUE
{
- bool b;
-
- b = dmaStreamAllocate(i2cp->rx.dma,
- STM32_I2C_I2C3_IRQ_PRIORITY,
- NULL,
- (void *)i2cp);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(i2cp->tx.dma,
- STM32_I2C_I2C3_IRQ_PRIORITY,
- NULL,
- (void *)i2cp);
- osalDbgAssert(!b, "stream already allocated");
+ i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C3_RX_DMA_CHANNEL,
+ STM32_I2C_I2C3_IRQ_PRIORITY,
+ NULL,
+ NULL);
+ osalDbgAssert(i2cp->rx.dma != NULL, "unable to allocate stream");
+ i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C3_TX_DMA_CHANNEL,
+ STM32_I2C_I2C3_IRQ_PRIORITY,
+ NULL,
+ NULL);
+ osalDbgAssert(i2cp->tx.dma != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
i2cp->txdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
@@ -910,18 +904,16 @@ void i2c_lld_start(I2CDriver *i2cp) { rccEnableI2C4(true);
#if STM32_I2C_USE_DMA == TRUE
{
- bool b;
-
- b = dmaStreamAllocate(i2cp->rx.dma,
- STM32_I2C_I2C4_IRQ_PRIORITY,
- NULL,
- (void *)i2cp);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(i2cp->tx.dma,
- STM32_I2C_I2C4_IRQ_PRIORITY,
- NULL,
- (void *)i2cp);
- osalDbgAssert(!b, "stream already allocated");
+ i2cp->rx.bdma = bdmaStreamAllocI(STM32_I2C_I2C4_RX_BDMA_CHANNEL,
+ STM32_I2C_I2C4_IRQ_PRIORITY,
+ NULL,
+ NULL);
+ osalDbgAssert(i2cp->rx.bdma != NULL, "unable to allocate stream");
+ i2cp->tx.bdma = bdmaStreamAllocI(STM32_I2C_I2C4_TX_BDMA_CHANNEL,
+ STM32_I2C_I2C4_IRQ_PRIORITY,
+ NULL,
+ NULL);
+ osalDbgAssert(i2cp->tx.bdma != NULL, "unable to allocate stream");
i2cp->rxdmamode |= STM32_BDMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
i2cp->txdmamode |= STM32_BDMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c index 994c31d14..2831c1810 100644 --- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c @@ -364,8 +364,8 @@ void spi_lld_init(void) { #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
SPID1.is_bdma = false;
#endif
- SPID1.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_CHANNEL);
- SPID1.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_CHANNEL);
+ SPID1.rx.dma = NULL;
+ SPID1.tx.dma = NULL;
SPID1.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@@ -386,8 +386,8 @@ void spi_lld_init(void) { #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
SPID2.is_bdma = false;
#endif
- SPID2.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_CHANNEL);
- SPID2.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_CHANNEL);
+ SPID2.rx.dma = NULL;
+ SPID2.tx.dma = NULL;
SPID2.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@@ -408,8 +408,8 @@ void spi_lld_init(void) { #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
SPID3.is_bdma = false;
#endif
- SPID3.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_CHANNEL);
- SPID3.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_CHANNEL);
+ SPID3.rx.dma = NULL;
+ SPID3.tx.dma = NULL;
SPID3.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@@ -430,8 +430,8 @@ void spi_lld_init(void) { #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
SPID4.is_bdma = false;
#endif
- SPID4.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_CHANNEL);
- SPID4.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_CHANNEL);
+ SPID4.rx.dma = NULL;
+ SPID4.tx.dma = NULL;
SPID4.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@@ -452,8 +452,8 @@ void spi_lld_init(void) { #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
SPID5.is_bdma = false;
#endif
- SPID5.rx.dma = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_CHANNEL);
- SPID5.tx.dma = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_CHANNEL);
+ SPID5.rx.dma = NULL;
+ SPID5.tx.dma = NULL;
SPID5.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
@@ -474,8 +474,8 @@ void spi_lld_init(void) { #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
SPID6.is_bdma = true;
#endif
- SPID6.rx.bdma = STM32_BDMA_STREAM(STM32_SPI_SPI6_RX_BDMA_CHANNEL);
- SPID6.tx.bdma = STM32_BDMA_STREAM(STM32_SPI_SPI6_TX_BDMA_CHANNEL);
+ SPID6.rx.bdma = NULL;
+ SPID6.tx.bdma = NULL;
SPID6.rxdmamode = STM32_BDMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_BDMA_CR_DIR_P2M |
STM32_BDMA_CR_TCIE |
@@ -503,17 +503,16 @@ void spi_lld_start(SPIDriver *spip) { if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
- bool b;
- b = dmaStreamAllocate(spip->rx.dma,
- STM32_SPI_SPI1_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(spip->tx.dma,
- STM32_SPI_SPI1_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
+ spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI1_RX_DMA_CHANNEL,
+ STM32_SPI_SPI1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
+ spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI1_TX_DMA_CHANNEL,
+ STM32_SPI_SPI1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->tx.dma!= NULL, "unable to allocate stream");
rccEnableSPI1(true);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI1_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI1_TX);
@@ -521,17 +520,16 @@ void spi_lld_start(SPIDriver *spip) { #endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
- bool b;
- b = dmaStreamAllocate(spip->rx.dma,
- STM32_SPI_SPI2_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(spip->tx.dma,
- STM32_SPI_SPI2_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
+ spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI2_RX_DMA_CHANNEL,
+ STM32_SPI_SPI2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
+ spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI2_TX_DMA_CHANNEL,
+ STM32_SPI_SPI2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->tx.dma!= NULL, "unable to allocate stream");
rccEnableSPI2(true);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI2_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI2_TX);
@@ -539,17 +537,16 @@ void spi_lld_start(SPIDriver *spip) { #endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
- bool b;
- b = dmaStreamAllocate(spip->rx.dma,
- STM32_SPI_SPI3_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(spip->tx.dma,
- STM32_SPI_SPI3_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
+ spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI3_RX_DMA_CHANNEL,
+ STM32_SPI_SPI3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
+ spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI3_TX_DMA_CHANNEL,
+ STM32_SPI_SPI3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->tx.dma!= NULL, "unable to allocate stream");
rccEnableSPI3(true);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI3_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI3_TX);
@@ -557,17 +554,16 @@ void spi_lld_start(SPIDriver *spip) { #endif
#if STM32_SPI_USE_SPI4
if (&SPID4 == spip) {
- bool b;
- b = dmaStreamAllocate(spip->rx.dma,
- STM32_SPI_SPI4_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(spip->tx.dma,
- STM32_SPI_SPI4_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
+ spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI4_RX_DMA_CHANNEL,
+ STM32_SPI_SPI4_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
+ spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI4_TX_DMA_CHANNEL,
+ STM32_SPI_SPI4_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->tx.dma!= NULL, "unable to allocate stream");
rccEnableSPI4(true);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI4_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI4_TX);
@@ -575,17 +571,16 @@ void spi_lld_start(SPIDriver *spip) { #endif
#if STM32_SPI_USE_SPI5
if (&SPID5 == spip) {
- bool b;
- b = dmaStreamAllocate(spip->rx.dma,
- STM32_SPI_SPI5_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
- b = dmaStreamAllocate(spip->tx.dma,
- STM32_SPI_SPI5_IRQ_PRIORITY,
- (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
+ spip->rx.dma = dmaStreamAllocI(STM32_SPI_SPI5_RX_DMA_CHANNEL,
+ STM32_SPI_SPI5_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
+ spip->tx.dma = dmaStreamAllocI(STM32_SPI_SPI5_TX_DMA_CHANNEL,
+ STM32_SPI_SPI5_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->tx.dma!= NULL, "unable to allocate stream");
rccEnableSPI5(true);
dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI5_RX);
dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI5_TX);
@@ -593,17 +588,16 @@ void spi_lld_start(SPIDriver *spip) { #endif
#if STM32_SPI_USE_SPI6
if (&SPID6 == spip) {
- bool b;
- b = bdmaStreamAllocate(spip->rx.bdma,
- STM32_SPI_SPI6_IRQ_PRIORITY,
- (stm32_bdmaisr_t)spi_lld_serve_bdma_rx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
- b = bdmaStreamAllocate(spip->tx.bdma,
- STM32_SPI_SPI6_IRQ_PRIORITY,
- (stm32_bdmaisr_t)spi_lld_serve_bdma_tx_interrupt,
- (void *)spip);
- osalDbgAssert(!b, "stream already allocated");
+ spip->rx.bdma = bdmaStreamAllocI(STM32_SPI_SPI6_RX_BDMA_CHANNEL,
+ STM32_SPI_SPI6_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_bdma_rx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->rx.dma != NULL, "unable to allocate stream");
+ spip->tx.bdma = bdmaStreamAllocI(STM32_SPI_SPI6_TX_BDMA_CHANNEL,
+ STM32_SPI_SPI6_IRQ_PRIORITY,
+ (stm32_dmaisr_t)spi_lld_serve_bdma_tx_interrupt,
+ (void *)spip);
+ osalDbgAssert(spip->tx.dma!= NULL, "unable to allocate stream");
rccEnableSPI6(true);
bdmaSetRequestSource(spip->rx.bdma, STM32_DMAMUX2_SPI6_RX);
bdmaSetRequestSource(spip->tx.bdma, STM32_DMAMUX2_SPI6_TX);
diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h index 26b30f9b0..7957c13df 100644 --- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h +++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h @@ -180,77 +180,77 @@ * @brief SPI1 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI1_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL 10
+#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI1 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI1_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL 11
+#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI2 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI2_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL 12
+#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI2 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI2_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL 13
+#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI3 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI3_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL 10
+#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI3 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI3_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL 11
+#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI4 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI4_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI4_RX_DMA_CHANNEL 12
+#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI4 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI4_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI4_TX_DMA_CHANNEL 13
+#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI5 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI5_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI5_RX_DMA_CHANNEL 12
+#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI5 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI5_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI5_TX_DMA_CHANNEL 13
+#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
#endif
/**
* @brief SPI6 RX BDMA channel setting.
*/
#if !defined(STM32_SPI_SPI6_RX_BDMA_CHANNEL) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI6_RX_BDMA_CHANNEL 2
+#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
#endif
/**
diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h index 00132cdb4..96ed7b079 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h @@ -226,7 +226,7 @@ #define STM32_HAS_SPI5 TRUE
#define STM32_SPI5_SUPPORTS_I2S FALSE
-#define STM32_SPI5_HANDLER Vector164
+#define STM32_SPI5_HANDLER Vector194
#define STM32_SPI5_NUMBER 85
#define STM32_HAS_SPI6 TRUE
|