diff options
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/STM32F3xx/platform.mk | 6 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F3xx/stm32_rcc.h | 54 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F3xx/stm32f30x.h | 7 |
3 files changed, 63 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F3xx/platform.mk b/os/hal/platforms/STM32F3xx/platform.mk index 8384b9717..6b02db68a 100644 --- a/os/hal/platforms/STM32F3xx/platform.mk +++ b/os/hal/platforms/STM32F3xx/platform.mk @@ -7,11 +7,13 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c
+ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F3xx \
${CHIBIOS}/os/hal/platforms/STM32 \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv2
+ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2 \
+ ${CHIBIOS}/os/hal/platforms/STM32/USBv1
diff --git a/os/hal/platforms/STM32F3xx/stm32_rcc.h b/os/hal/platforms/STM32F3xx/stm32_rcc.h index 8d4ec20d3..7c4b30466 100644 --- a/os/hal/platforms/STM32F3xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F3xx/stm32_rcc.h @@ -662,6 +662,60 @@ * @api
*/
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
/** @} */
/**
diff --git a/os/hal/platforms/STM32F3xx/stm32f30x.h b/os/hal/platforms/STM32F3xx/stm32f30x.h index 4e3dc9aa1..bbb297f80 100644 --- a/os/hal/platforms/STM32F3xx/stm32f30x.h +++ b/os/hal/platforms/STM32F3xx/stm32f30x.h @@ -4752,8 +4752,11 @@ typedef struct #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART3EN ((uint32_t)0x00080000) /*!< UART 3 clock enable */
-#define RCC_APB1ENR_UART4EN ((uint32_t)0x00100000) /*!< UART 4 clock enable */
+/* CHIBIOS FIX */
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 3 clock enable */
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 4 clock enable */
+//#define RCC_APB1ENR_UART3EN ((uint32_t)0x00080000) /*!< UART 3 clock enable */
+//#define RCC_APB1ENR_UART4EN ((uint32_t)0x00100000) /*!< UART 4 clock enable */
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
|