diff options
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c | 28 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h | 17 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/stm32_registry.h | 4 |
3 files changed, 44 insertions, 5 deletions
diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c index d395e0b43..fd1b649fb 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c @@ -89,6 +89,27 @@ static void qspi_lld_serve_interrupt(QSPIDriver *qspip) { /* Driver interrupt handlers. */
/*===========================================================================*/
+#if STM32_QSPI_USE_QUADSPI1 || defined(__DOXYGEN__)
+#if !defined(STM32_QUADSPI1_SUPPRESS_ISR)
+#if !defined(STM32_QUADSPI1_HANDLER)
+#error "STM32_QUADSPI1_HANDLER not defined"
+#endif
+/**
+ * @brief STM32_QUADSPI1_HANDLER interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_QUADSPI1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ qspi_lld_serve_interrupt(&QSPID1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* !defined(STM32_QUADSPI1_SUPPRESS_ISR) */
+#endif /* STM32_QSPI_USE_QUADSPI1 */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -111,6 +132,7 @@ void qspi_lld_init(void) { STM32_DMA_CR_MINC |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
+ nvicEnableVector(STM32_QUADSPI1_NUMBER, STM32_QSPI_QUADSPI1_IRQ_PRIORITY);
#endif
}
@@ -128,7 +150,7 @@ void qspi_lld_start(QSPIDriver *qspip) { #if STM32_QSPI_USE_QUADSPI1
if (&QSPID1 == qspip) {
bool b = dmaStreamAllocate(qspip->dma,
- STM32_QSPI_QUADSPI1_IRQ_PRIORITY,
+ STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)qspi_lld_serve_dma_interrupt,
(void *)qspip);
osalDbgAssert(!b, "stream already allocated");
@@ -186,10 +208,8 @@ void qspi_lld_stop(QSPIDriver *qspip) { */
void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp) {
+ qspip->qspi->ABR = cmdp->alt;
qspip->qspi->CCR = cmdp->cfg;
- if ((cmdp->cfg & QSPI_CFG_ALT_MODE_MASK) != QSPI_CFG_ALT_MODE_NONE) {
- qspip->qspi->ABR = cmdp->alt;
- }
if ((cmdp->cfg & QSPI_CFG_ADDR_MODE_MASK) != QSPI_CFG_ADDR_MODE_NONE) {
qspip->qspi->AR = cmdp->addr;
}
diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h index 100572dfc..fb52ed7b8 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h @@ -73,6 +73,13 @@ #endif
/**
+ * @brief QUADSPI1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY 10
+#endif
+
+/**
* @brief QUADSPI DMA error hook.
*/
#if !defined(STM32_QSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
@@ -98,10 +105,20 @@ #endif
#if STM32_QSPI_USE_QUADSPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to QUADSPI1 DMA"
+#endif
+
+#if STM32_QSPI_USE_QUADSPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to QUADSPI1"
#endif
+#if (STM32_QSPI_QUADSPI1_PRESCALER_VALUE < 1) || \
+ (STM32_QSPI_QUADSPI1_PRESCALER_VALUE > 256)
+#error "STM32_QSPI_QUADSPI1_PRESCALER_VALUE not within 1..256"
+#endif
+
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h index 09de989ca..f39d3e882 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -211,9 +211,11 @@ /* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector15C
+#define STM32_QUADSPI1_NUMBER 71
#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_QUADSPI1_DMA_CHN 0x03000000
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
|