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-rw-r--r--os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c33
-rw-r--r--os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h33
-rw-r--r--os/hal/ports/STM32/STM32F7xx/hal_lld.c12
-rw-r--r--os/hal/ports/STM32/STM32F7xx/hal_lld.h46
4 files changed, 87 insertions, 37 deletions
diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
index bf2398711..b88e9b041 100644
--- a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
+++ b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
@@ -28,14 +28,6 @@
#if HAL_USE_SDC || defined(__DOXYGEN__)
-#if !defined(STM32_SDMMCCLK)
-#error "STM32_SDMMCCLK not defined"
-#endif
-
-#if STM32_SDMMCCLK > 48000000
-#error "STM32_SDMMCCLK exceeding 48MHz"
-#endif
-
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
@@ -56,11 +48,18 @@
#define SDMMC_CLKDIV_HS (2 - 2)
#define SDMMC_CLKDIV_LS (120 - 2)
-#define SDMMC_WRITE_TIMEOUT \
- (((STM32_SDMMCCLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \
+#define SDMMC1_WRITE_TIMEOUT \
+ (((STM32_SDMMC1CLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \
+ STM32_SDC_SDMMC_WRITE_TIMEOUT)
+#define SDMMC1_READ_TIMEOUT \
+ (((STM32_SDMMC1CLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \
+ STM32_SDC_SDMMC_READ_TIMEOUT)
+
+#define SDMMC2_WRITE_TIMEOUT \
+ (((STM32_SDMMC2CLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \
STM32_SDC_SDMMC_WRITE_TIMEOUT)
-#define SDMMC_READ_TIMEOUT \
- (((STM32_SDMMCCLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \
+#define SDMMC2_READ_TIMEOUT \
+ (((STM32_SDMMC2CLK / (SDMMC_CLKDIV_HS + 2)) / 1000) * \
STM32_SDC_SDMMC_READ_TIMEOUT)
#define SDMMC1_DMA_CHANNEL \
@@ -129,7 +128,7 @@ static bool sdc_lld_prepare_read_bytes(SDCDriver *sdcp,
uint8_t *buf, uint32_t bytes) {
osalDbgCheck(bytes < 0x1000000);
- sdcp->sdmmc->DTIMER = SDMMC_READ_TIMEOUT;
+ sdcp->sdmmc->DTIMER = sdcp->rtmo;
/* Checks for errors and waits for the card to be ready for reading.*/
if (_sdc_wait_for_transfer_state(sdcp))
@@ -396,6 +395,8 @@ void sdc_lld_init(void) {
#if STM32_SDC_USE_SDMMC1
sdcObjectInit(&SDCD1);
SDCD1.thread = NULL;
+ SDCD1.rtmo = SDMMC1_READ_TIMEOUT;
+ SDCD1.wtmo = SDMMC1_WRITE_TIMEOUT;
SDCD1.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC1_DMA_STREAM);
SDCD1.sdmmc = SDMMC1;
nvicEnableVector(STM32_SDMMC1_NUMBER, STM32_SDC_SDMMC1_IRQ_PRIORITY);
@@ -404,6 +405,8 @@ void sdc_lld_init(void) {
#if STM32_SDC_USE_SDMMC2
sdcObjectInit(&SDCD2);
SDCD2.thread = NULL;
+ SDCD2.rtmo = SDMMC2_READ_TIMEOUT;
+ SDCD2.wtmo = SDMMC2_WRITE_TIMEOUT;
SDCD2.dma = STM32_DMA_STREAM(STM32_SDC_SDMMC2_DMA_STREAM);
SDCD2.sdmmc = SDMMC2;
nvicEnableVector(STM32_SDMMC2_NUMBER, STM32_SDC_SDMMC2_IRQ_PRIORITY);
@@ -789,7 +792,7 @@ bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE);
- sdcp->sdmmc->DTIMER = SDMMC_READ_TIMEOUT;
+ sdcp->sdmmc->DTIMER = sdcp->rtmo;
/* Checks for errors and waits for the card to be ready for reading.*/
if (_sdc_wait_for_transfer_state(sdcp))
@@ -850,7 +853,7 @@ bool sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE);
- sdcp->sdmmc->DTIMER = SDMMC_WRITE_TIMEOUT;
+ sdcp->sdmmc->DTIMER = sdcp->wtmo;
/* Checks for errors and waits for the card to be ready for writing.*/
if (_sdc_wait_for_transfer_state(sdcp))
diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
index 7a6c2351f..44af62ab3 100644
--- a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
+++ b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
@@ -161,16 +161,33 @@
#endif
/* Clock related tests.*/
-#if !defined(STM32_SDMMCCLK)
-#error "STM32_SDMMCCLK not defined"
+#if STM32_HAS_SDMMC1 && !defined(STM32_SDMMC1CLK)
+#error "STM32_SDMMC1CLK not defined"
+#endif
+
+/* Clock related tests.*/
+#if STM32_HAS_SDMMC2 && !defined(STM32_SDMMC2CLK)
+#error "STM32_SDMMC2CLK not defined"
#endif
#if !defined(STM32_HCLK)
#error "STM32_HCLK not defined"
#endif
-#if STM32_SDMMCCLK * 10 > STM32_HCLK * 7
-#error "STM32_SDC_USE_SDMMC1 must not exceed STM32_HCLK * 0.7"
+#if STM32_HAS_SDMMC1 && (STM32_SDMMC1CLK * 10 > STM32_HCLK * 7)
+#error "STM32_SDMMC1CLK must not exceed STM32_HCLK * 0.7"
+#endif
+
+#if STM32_HAS_SDMMC2 && (STM32_SDMMC2CLK * 10 > STM32_HCLK * 7)
+#error "STM32_SDMMC2CLK must not exceed STM32_HCLK * 0.7"
+#endif
+
+#if STM32_HAS_SDMMC1 && (STM32_SDMMC1CLK > 48000000)
+#error "STM32_SDMMC1CLK must not exceed 48MHz"
+#endif
+
+#if STM32_HAS_SDMMC2 && (STM32_SDMMC2CLK > 48000000)
+#error "STM32_SDMMC2CLK must not exceed 48MHz"
#endif
/* SDMMC IRQ priority tests.*/
@@ -301,6 +318,14 @@ struct SDCDriver {
*/
thread_reference_t thread;
/**
+ * @brief DTIMER register value for read operations.
+ */
+ uint32_t rtmo;
+ /**
+ * @brief DTIMER register value for write operations.
+ */
+ uint32_t wtmo;
+ /**
* @brief DMA mode bit mask.
*/
uint32_t dmamode;
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
index 20af00675..74ab39734 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -279,12 +279,12 @@ void stm32_clock_init(void) {
}
/* Peripheral clock sources.*/
- RCC->DCKCFGR2 = STM32_SDMMCSEL | STM32_CK48MSEL | STM32_CECSEL |
- STM32_LPTIM1SEL | STM32_I2C4SEL | STM32_I2C3SEL |
- STM32_I2C2SEL | STM32_I2C1SEL | STM32_UART8SEL |
- STM32_UART7SEL | STM32_USART6SEL | STM32_UART5SEL |
- STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL |
- STM32_USART1SEL;
+ RCC->DCKCFGR2 = STM32_SDMMC2SEL | STM32_SDMMC1SEL | STM32_CK48MSEL |
+ STM32_CECSEL | STM32_LPTIM1SEL | STM32_I2C4SEL |
+ STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
+ STM32_UART8SEL | STM32_UART7SEL | STM32_USART6SEL |
+ STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
+ STM32_USART2SEL | STM32_USART1SEL;
/* Flash setup.*/
FLASH->ACR = FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS;
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h
index d84e2333f..d0c503361 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h
@@ -412,9 +412,13 @@
#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
-#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
-#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
-#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
+#define STM32_SDMMC1SEL_MASK (1 << 28) /**< SDMMC1SEL mask. */
+#define STM32_SDMMC1SEL_PLL48CLK (0 << 28) /**< SDMMC1 source is PLL48CLK. */
+#define STM32_SDMMC1SEL_SYSCLK (1 << 28) /**< SDMMC1 source is SYSCLK. */
+
+#define STM32_SDMMC2SEL_MASK (1 << 29) /**< SDMMC2SEL mask. */
+#define STM32_SDMMC2SEL_PLL48CLK (0 << 29) /**< SDMMC2 source is PLL48CLK. */
+#define STM32_SDMMC2SEL_SYSCLK (1 << 29) /**< SDMMC2 source is SYSCLK. */
/** @} */
/**
@@ -848,10 +852,17 @@
#endif
/**
- * @brief SDMMC clock source.
+ * @brief SDMMC1 clock source.
+ */
+#if !defined(STM32_SDMMC1SEL) || defined(__DOXYGEN__)
+#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
+#endif
+
+/**
+ * @brief SDMMC2 clock source.
*/
-#if !defined(STM32_SDMMCSEL) || defined(__DOXYGEN__)
-#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
+#if !defined(STM32_SDMMC2SEL) || defined(__DOXYGEN__)
+#define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK
#endif
/**
@@ -1961,14 +1972,25 @@
#endif
/**
- * @brief SDMMC frequency.
+ * @brief SDMMC1 frequency.
+ */
+#if (STM32_SDMMC1SEL == STM32_SDMMC1SEL_PLL48CLK) || defined(__DOXYGEN__)
+#define STM32_SDMMC1CLK STM32_PLL48CLK
+#elif STM32_SDMMC1SEL == STM32_SDMMCSEL_SYSCLK
+#define STM32_SDMMC1CLK STM32_SYSCLK
+#else
+#error "invalid source selected for SDMMC1 clock"
+#endif
+
+/**
+ * @brief SDMMC2 frequency.
*/
-#if (STM32_SDMMCSEL == STM32_SDMMCSEL_PLL48CLK) || defined(__DOXYGEN__)
-#define STM32_SDMMCCLK STM32_PLL48CLK
-#elif STM32_SDMMCSEL == STM32_SDMMCSEL_SYSCLK
-#define STM32_SDMMCCLK STM32_SYSCLK
+#if (STM32_SDMMC2SEL == STM32_SDMMC1SEL_PLL48CLK) || defined(__DOXYGEN__)
+#define STM32_SDMMC2CLK STM32_PLL48CLK
+#elif STM32_SDMMC2SEL == STM32_SDMMCSEL_SYSCLK
+#define STM32_SDMMC2CLK STM32_SYSCLK
#else
-#error "invalid source selected for SDMMC clock"
+#error "invalid source selected for SDMMC2 clock"
#endif
/**
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-06 03:39:06 +0000