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-rw-r--r--os/ports/RVCT/ARMCMx/chcore_v7m.h165
1 files changed, 122 insertions, 43 deletions
diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h
index 7f7d8c5be..14b25fd8c 100644
--- a/os/ports/RVCT/ARMCMx/chcore_v7m.h
+++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h
@@ -30,9 +30,111 @@
#define _CHCORE_V7M_H_
/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED 0
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief Simplified priority handling flag.
+ * @details Activating this option will make the Kernel work in compact mode.
+ */
+#ifndef CORTEX_SIMPLIFIED_PRIORITY
+#define CORTEX_SIMPLIFIED_PRIORITY FALSE
+#endif
+
+/**
+ * @brief SVCALL handler priority.
+ * @note The default SVCALL handler priority is defaulted to
+ * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
+ * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
+ * priority level.
+ */
+#ifndef CORTEX_PRIORITY_SVCALL
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
+#else
+/* If it is externally redefined then better perform a validity check on it.*/
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
+#endif
+#endif
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief BASEPRI level within kernel lock.
+ * @note In compact kernel mode this constant value is enforced to zero.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define CORTEX_BASEPRI_KERNEL \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
+#else
+#define CORTEX_BASEPRI_KERNEL 0
+#endif
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,
+ * this handler always have the highest priority that cannot preempt
+ * the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define CH_ARCHITECTURE_ARM_v7M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "ARMv7-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define CH_CORE_VARIANT_NAME "Cortex-M3"
+
+#elif (CORTEX_MODEL == CORTEX_M4)
+#define CH_ARCHITECTURE_ARM_v7ME
+#define CH_ARCHITECTURE_NAME "ARMv7-ME"
+#define CH_CORE_VARIANT_NAME "Cortex-M4"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define CH_PORT_INFO "Advanced kernel mode"
+#else
+#define CH_PORT_INFO "Compact kernel mode"
+#endif
+
+/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -59,48 +161,6 @@ struct intctx {
#endif
/**
- * @brief Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = (void *)pf; \
- tp->p_ctx.r13->r5 = arg; \
- tp->p_ctx.r13->lr = (void *)_port_thread_start; \
-}
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p PORT_INT_REQUIRED_STACK.
- * @note In this port it is set to 16 because the idle thread does have
- * a stack frame when compiling without optimizations. You may
- * reduce this value to zero when compiling with optimizations.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE 16
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
- * compiler optimizations disabled.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK 16
-#endif
-
-/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
@@ -135,6 +195,8 @@ struct intctx {
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_SVCALL, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
@@ -145,10 +207,14 @@ struct intctx {
* more actions.
* @note In this port this it raises the base priority to kernel level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_lock() { \
register uint32_t basepri __asm("basepri"); \
basepri = CORTEX_BASEPRI_KERNEL; \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_lock() __disable_irq()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-unlock action.
@@ -156,10 +222,14 @@ struct intctx {
* more actions.
* @note In this port this it lowers the base priority to user level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_unlock() { \
register uint32_t basepri __asm("basepri"); \
basepri = CORTEX_BASEPRI_DISABLED; \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_unlock() __enable_irq()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-lock action from an interrupt handler.
@@ -192,21 +262,28 @@ struct intctx {
* @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_suspend() { \
register uint32_t basepri __asm("basepri"); \
basepri = CORTEX_BASEPRI_KERNEL; \
- __enable_irq(); \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_suspend() __disable_irq()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_enable() { \
register uint32_t basepri __asm("basepri"); \
basepri = CORTEX_BASEPRI_DISABLED; \
__enable_irq(); \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_enable() __enable_irq()
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
@@ -255,6 +332,8 @@ extern "C" {
}
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V7M_H_ */
/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 01:11:25 +0000