diff options
Diffstat (limited to 'os/ports/GCC/PPC/SPC564Axx')
| -rw-r--r-- | os/ports/GCC/PPC/SPC564Axx/core.s | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/os/ports/GCC/PPC/SPC564Axx/core.s b/os/ports/GCC/PPC/SPC564Axx/core.s index 36b5575d6..92232a9fa 100644 --- a/os/ports/GCC/PPC/SPC564Axx/core.s +++ b/os/ports/GCC/PPC/SPC564Axx/core.s @@ -35,6 +35,15 @@ /** @} */
/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
* @name BUCSR default settings
* @{
*/
@@ -42,6 +51,13 @@ /** @} */
/**
+ * @name LICSR1 default settings
+ * @{
+ */
+#define LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+/** @} */
+
+/**
* @name MSR register definitions
* @{
*/
@@ -132,6 +148,18 @@ _coreinit: li %r3, BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
+ /*
+ * Cache invalidated and then enabled.
+ */
+ li %r3, LICSR1_ICINV
+ mtspr 1011, %r3 /* LICSR1 */
+.inv: mfspr %r3, 1011 /* LICSR1 */
+ andi. %r3, %r3, LICSR1_ICINV
+ bne .inv
+ lis %r3, LICSR1_DEFAULT@h
+ ori %r3, %r3, LICSR1_DEFAULT@l
+ mtspr 1011, %r3 /* LICSR1 */
+
blr
/*
|