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-rw-r--r--os/ports/GCC/ARMCMx/LPC11xx/cmparams.h2
-rw-r--r--os/ports/GCC/ARMCMx/LPC13xx/cmparams.h2
-rw-r--r--os/ports/GCC/ARMCMx/STM32/cmparams.h2
-rw-r--r--os/ports/GCC/ARMCMx/STM32/vectors.c2
-rw-r--r--os/ports/GCC/ARMCMx/chcore.h52
-rw-r--r--os/ports/GCC/ARMCMx/port.dox15
6 files changed, 42 insertions, 33 deletions
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h
index f5bf1e3fb..b3dfd2949 100644
--- a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h
+++ b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h
@@ -22,7 +22,7 @@
* @brief ARM Cortex-M0 LPC11xx Specific Parameters.
*
* @defgroup ARMCMx_LPC11xx LPC11xx Specific Parameters
- * @ingroup ARMCMx
+ * @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* LPC11xx platform.
* @{
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h
index bc8d76b77..1822647d3 100644
--- a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h
+++ b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h
@@ -22,7 +22,7 @@
* @brief ARM Cortex-M3 LPC13xx Specific Parameters.
*
* @defgroup ARMCMx_LPC13xx LPC13xx Specific Parameters
- * @ingroup ARMCMx
+ * @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
* LPC13xx platform.
* @{
diff --git a/os/ports/GCC/ARMCMx/STM32/cmparams.h b/os/ports/GCC/ARMCMx/STM32/cmparams.h
index 06dfa8954..de07b7c67 100644
--- a/os/ports/GCC/ARMCMx/STM32/cmparams.h
+++ b/os/ports/GCC/ARMCMx/STM32/cmparams.h
@@ -22,7 +22,7 @@
* @brief ARM Cortex-M3 parameters for the STM32.
*
* @defgroup ARMCMx_STM32 STM32 Specific Parameters
- * @ingroup ARMCMx
+ * @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
* STM32 platform.
* @{
diff --git a/os/ports/GCC/ARMCMx/STM32/vectors.c b/os/ports/GCC/ARMCMx/STM32/vectors.c
index 59bad352b..d2306add0 100644
--- a/os/ports/GCC/ARMCMx/STM32/vectors.c
+++ b/os/ports/GCC/ARMCMx/STM32/vectors.c
@@ -22,7 +22,7 @@
* @brief Interrupt vectors for the STM32 family.
*
* @defgroup ARMCMx_STM32_VECTORS STM32 Interrupt Vectors
- * @ingroup ARMCMx
+ * @ingroup ARMCMx_SPECIFIC
* @details Interrupt vectors for the STM32 family.
* @{
*/
diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h
index db02d6bc1..41d433508 100644
--- a/os/ports/GCC/ARMCMx/chcore.h
+++ b/os/ports/GCC/ARMCMx/chcore.h
@@ -34,10 +34,10 @@
/* Port constants. */
/*===========================================================================*/
-#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
-#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
-#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
-#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
+#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
+#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
+#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
+#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
@@ -57,26 +57,26 @@
/**
* @brief Total priority levels.
*/
-#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
+#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
/**
* @brief Minimum priority level.
* @details This minimum priority level is calculated from the number of
* priority bits supported by the specific Cortex-Mx implementation.
*/
-#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
/**
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
-#define CORTEX_MAXIMUM_PRIORITY 0
+#define CORTEX_MAXIMUM_PRIORITY 0
/**
* @brief Disabled value for BASEPRI register.
* @note ARMv7-M architecture only.
*/
-#define CORTEX_BASEPRI_DISABLED 0
+#define CORTEX_BASEPRI_DISABLED 0
/*===========================================================================*/
/* Port macros. */
@@ -91,7 +91,8 @@
/**
* @brief Priority level to priority mask conversion macro.
*/
-#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
+#define CORTEX_PRIORITY_MASK(n) \
+ ((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/
/* Port configurable parameters. */
@@ -101,7 +102,7 @@
* @brief Enables the use of the WFI instruction in the idle thread loop.
*/
#ifndef CORTEX_ENABLE_WFI_IDLE
-#define CORTEX_ENABLE_WFI_IDLE FALSE
+#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
@@ -110,7 +111,7 @@
* level in the middle of the numeric priorities range.
*/
#ifndef CORTEX_PRIORITY_SYSTICK
-#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
+#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
#else
/* If it is externally redefined then better perform a validity check on it.*/
#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
@@ -128,7 +129,7 @@
* to user in the ARMv6-M port.
*/
#ifndef CORTEX_PRIORITY_SVCALL
-#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
#else
/* If it is externally redefined then better perform a validity check on it.*/
#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
@@ -146,7 +147,7 @@
* the minimum priority level.
*/
#ifndef CORTEX_PRIORITY_PENDSV
-#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY
+#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY
#else
/* If it is externally redefined then better perform a validity check on it.*/
#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV)
@@ -161,7 +162,8 @@
* @note ARMv7-M architecture only.
*/
#ifndef CORTEX_BASEPRI_KERNEL
-#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
+#define CORTEX_BASEPRI_KERNEL \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
#endif
/**
@@ -172,7 +174,7 @@
* @note Allowed values are 32 or 64.
*/
#ifndef CORTEX_STACK_ALIGNMENT
-#define CORTEX_STACK_ALIGNMENT 64
+#define CORTEX_STACK_ALIGNMENT 64
#endif
/*===========================================================================*/
@@ -204,7 +206,7 @@
* - "ARMv7-ME".
* .
*/
-#define CH_ARCHITECTURE_NAME "ARMvx-M"
+#define CH_ARCHITECTURE_NAME "ARMvx-M"
/**
* @brief Name of the architecture variant (optional).
@@ -216,24 +218,24 @@
* - "Cortex-M4"
* .
*/
-#define CH_CORE_VARIANT_NAME "Cortex-Mx"
+#define CH_CORE_VARIANT_NAME "Cortex-Mx"
#elif CORTEX_MODEL == CORTEX_M4
#define CH_ARCHITECTURE_ARM_v7M
-#define CH_ARCHITECTURE_NAME "ARMv7-ME"
-#define CH_CORE_VARIANT_NAME "Cortex-M4"
+#define CH_ARCHITECTURE_NAME "ARMv7-ME"
+#define CH_CORE_VARIANT_NAME "Cortex-M4"
#elif CORTEX_MODEL == CORTEX_M3
#define CH_ARCHITECTURE_ARM_v7M
-#define CH_ARCHITECTURE_NAME "ARMv7-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M3"
+#define CH_ARCHITECTURE_NAME "ARMv7-M"
+#define CH_CORE_VARIANT_NAME "Cortex-M3"
#elif CORTEX_MODEL == CORTEX_M1
#define CH_ARCHITECTURE_ARM_v6M
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M1"
+#define CH_ARCHITECTURE_NAME "ARMv6-M"
+#define CH_CORE_VARIANT_NAME "Cortex-M1"
#elif CORTEX_MODEL == CORTEX_M0
#define CH_ARCHITECTURE_ARM_v6M
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M0"
+#define CH_ARCHITECTURE_NAME "ARMv6-M"
+#define CH_CORE_VARIANT_NAME "Cortex-M0"
#endif
/*===========================================================================*/
diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox
index 2f91f27f3..adfd49981 100644
--- a/os/ports/GCC/ARMCMx/port.dox
+++ b/os/ports/GCC/ARMCMx/port.dox
@@ -135,7 +135,7 @@
* structures.
* - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
* thread. Usually there is no need to change this value unless inserting
- * code in the IDLE thread hook macro.
+ * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
* code. Code running at higher priority levels must not invoke any OS API.
* This setting is specific to the ARMv7-M architecture.
@@ -143,9 +143,9 @@
* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
- * @p <b>wfi</b> instruction from within the idle loop. This is defaulted to
- * FALSE because it can create problems with some debuggers. Setting this
- * option to TRUE reduces the system power requirements.
+ * @p <b>wfi</b> instruction from within the idle loop. This option is
+ * defaulted to FALSE because it can create problems with some debuggers.
+ * Setting this option to TRUE reduces the system power requirements.
* .
* @ingroup ARMCMx
*/
@@ -219,3 +219,10 @@
*
* @ingroup ARMCMx
*/
+
+/**
+ * @defgroup ARMCMx_SPECIFIC Specific Implementations
+ * @details Platform-specific port code.
+ *
+ * @ingroup ARMCMx
+ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-28 07:51:29 +0000