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Diffstat (limited to 'os/halnew/platforms/STM32F30x/stm32_dma.c')
-rw-r--r--os/halnew/platforms/STM32F30x/stm32_dma.c81
1 files changed, 40 insertions, 41 deletions
diff --git a/os/halnew/platforms/STM32F30x/stm32_dma.c b/os/halnew/platforms/STM32F30x/stm32_dma.c
index 71777583d..6b09cceb3 100644
--- a/os/halnew/platforms/STM32F30x/stm32_dma.c
+++ b/os/halnew/platforms/STM32F30x/stm32_dma.c
@@ -29,7 +29,6 @@
* @{
*/
-#include "ch.h"
#include "hal.h"
/* The following macro is only defined if some driver requiring DMA services
@@ -116,17 +115,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
*
* @isr
*/
-CH_IRQ_HANDLER(Vector6C) {
+OSAL_IRQ_HANDLER(Vector6C) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[0].dma_func)
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -134,17 +133,17 @@ CH_IRQ_HANDLER(Vector6C) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector70) {
+OSAL_IRQ_HANDLER(Vector70) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
if (dma_isr_redir[1].dma_func)
dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -152,17 +151,17 @@ CH_IRQ_HANDLER(Vector70) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector74) {
+OSAL_IRQ_HANDLER(Vector74) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
if (dma_isr_redir[2].dma_func)
dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -170,17 +169,17 @@ CH_IRQ_HANDLER(Vector74) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector78) {
+OSAL_IRQ_HANDLER(Vector78) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
if (dma_isr_redir[3].dma_func)
dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -188,17 +187,17 @@ CH_IRQ_HANDLER(Vector78) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector7C) {
+OSAL_IRQ_HANDLER(Vector7C) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[4].dma_func)
dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -206,17 +205,17 @@ CH_IRQ_HANDLER(Vector7C) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector80) {
+OSAL_IRQ_HANDLER(Vector80) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
if (dma_isr_redir[5].dma_func)
dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -224,17 +223,17 @@ CH_IRQ_HANDLER(Vector80) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector84) {
+OSAL_IRQ_HANDLER(Vector84) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
if (dma_isr_redir[6].dma_func)
dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -242,17 +241,17 @@ CH_IRQ_HANDLER(Vector84) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector120) {
+OSAL_IRQ_HANDLER(Vector120) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[7].dma_func)
dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -260,17 +259,17 @@ CH_IRQ_HANDLER(Vector120) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector124) {
+OSAL_IRQ_HANDLER(Vector124) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
if (dma_isr_redir[8].dma_func)
dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -278,17 +277,17 @@ CH_IRQ_HANDLER(Vector124) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector128) {
+OSAL_IRQ_HANDLER(Vector128) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
if (dma_isr_redir[9].dma_func)
dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -296,17 +295,17 @@ CH_IRQ_HANDLER(Vector128) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector12C) {
+OSAL_IRQ_HANDLER(Vector12C) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
if (dma_isr_redir[10].dma_func)
dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -314,17 +313,17 @@ CH_IRQ_HANDLER(Vector12C) {
*
* @isr
*/
-CH_IRQ_HANDLER(Vector130) {
+OSAL_IRQ_HANDLER(Vector130) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[11].dma_func)
dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
@@ -379,7 +378,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
stm32_dmaisr_t func,
void *param) {
- chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
+ osalDbgCheck(dmastp != NULL);
/* Checks if the stream is already taken.*/
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
@@ -424,11 +423,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
- chDbgCheck(dmastp != NULL, "dmaStreamRelease");
+ osalDbgCheck(dmastp != NULL);
/* Check if the streams is not taken.*/
- chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
- "dmaStreamRelease(), #1", "not allocated");
+ osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+ "dmaStreamRelease(), #1", "not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector);
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-15 15:49:55 +0000