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-rw-r--r--os/hal/platforms/STM32/icu_lld.c12
-rw-r--r--os/hal/platforms/STM32/icu_lld.h4
-rw-r--r--os/hal/platforms/STM32/pwm_lld.c18
-rw-r--r--os/hal/platforms/STM32F1xx/hal_lld.h59
-rw-r--r--os/hal/platforms/STM32F1xx/stm32f10x.h3
-rw-r--r--os/hal/platforms/STM32F4xx/hal_lld.h41
-rw-r--r--os/hal/platforms/STM32F4xx/stm32f4xx.h3
-rw-r--r--os/hal/platforms/STM32L1xx/hal_lld.h55
-rw-r--r--os/hal/platforms/STM32L1xx/stm32l1xx.h3
9 files changed, 159 insertions, 39 deletions
diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c
index 33eff67d5..ab3e12f26 100644
--- a/os/hal/platforms/STM32/icu_lld.c
+++ b/os/hal/platforms/STM32/icu_lld.c
@@ -343,12 +343,12 @@ void icu_lld_start(ICUDriver *icup) {
}
else {
/* Driver re-configuration scenario, it must be stopped first.*/
- icup->tim->CR1 = 0; /* Timer disabled. */
- icup->tim->DIER = 0; /* All IRQs disabled. */
- icup->tim->SR = 0; /* Clear eventual pending IRQs. */
- icup->tim->CCR1 = 0; /* Comparator 1 disabled. */
- icup->tim->CCR2 = 0; /* Comparator 2 disabled. */
- icup->tim->CNT = 0; /* Counter reset to zero. */
+ icup->tim->CR1 = 0; /* Timer disabled. */
+ icup->tim->DIER = 0; /* All IRQs disabled. */
+ icup->tim->SR = 0; /* Clear eventual pending IRQs. */
+ icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */
+ icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */
+ icup->tim->CNT = 0; /* Counter reset to zero. */
}
/* Timer configuration.*/
diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h
index 3156023eb..b97930609 100644
--- a/os/hal/platforms/STM32/icu_lld.h
+++ b/os/hal/platforms/STM32/icu_lld.h
@@ -262,7 +262,7 @@ struct ICUDriver {
*
* @notapi
*/
-#define icu_lld_get_width(icup) ((icup)->tim->CCR2 + 1)
+#define icu_lld_get_width(icup) ((icup)->tim->CCR[1] + 1)
/**
* @brief Returns the width of the latest cycle.
@@ -274,7 +274,7 @@ struct ICUDriver {
*
* @notapi
*/
-#define icu_lld_get_period(icup) ((icup)->tim->CCR1 + 1)
+#define icu_lld_get_period(icup) ((icup)->tim->CCR[0] + 1)
/*===========================================================================*/
/* External declarations. */
diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c
index ab3c1c2bb..fb5d12adf 100644
--- a/os/hal/platforms/STM32/pwm_lld.c
+++ b/os/hal/platforms/STM32/pwm_lld.c
@@ -419,13 +419,13 @@ void pwm_lld_start(PWMDriver *pwmp) {
}
else {
/* Driver re-configuration scenario, it must be stopped first.*/
- pwmp->tim->CR1 = 0; /* Timer disabled. */
- pwmp->tim->DIER = 0; /* All IRQs disabled. */
- pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */
- pwmp->tim->CCR1 = 0; /* Comparator 1 disabled. */
- pwmp->tim->CCR2 = 0; /* Comparator 2 disabled. */
- pwmp->tim->CCR3 = 0; /* Comparator 3 disabled. */
- pwmp->tim->CCR4 = 0; /* Comparator 4 disabled. */
+ pwmp->tim->CR1 = 0; /* Timer disabled. */
+ pwmp->tim->DIER = 0; /* All IRQs disabled. */
+ pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */
+ pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */
+ pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */
+ pwmp->tim->CCR[2] = 0; /* Comparator 3 disabled. */
+ pwmp->tim->CCR[3] = 0; /* Comparator 4 disabled. */
pwmp->tim->CNT = 0; /* Counter reset to zero. */
}
@@ -599,7 +599,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
- *(&pwmp->tim->CCR1 + (channel * 2)) = width; /* New duty cycle. */
+ pwmp->tim->CCR[channel] = width; /* New duty cycle. */
/* If there is a callback defined for the channel then the associated
interrupt must be enabled.*/
if (pwmp->config->channels[channel].callback != NULL) {
@@ -627,7 +627,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
*/
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
- *(&pwmp->tim->CCR1 + (channel * 2)) = 0;
+ pwmp->tim->CCR[channel] = 0;
pwmp->tim->DIER &= ~(2 << channel);
}
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h
index 9b87b0a85..a4ccd3118 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld.h
@@ -43,6 +43,12 @@
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
+#include "stm32f10x.h"
+
+/* STM32 DMA and RCC helpers.*/
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@@ -100,6 +106,47 @@
/* Driver data structures and types. */
/*===========================================================================*/
+/**
+ * @brief STM32 TIM registers block.
+ * @note Removed from the ST headers and redefined because the non uniform
+ * declaration of the CCR registers among the various sub-families.
+ */
+typedef struct {
+ volatile uint16_t CR1;
+ uint16_t _resvd0;
+ volatile uint16_t CR2;
+ uint16_t _resvd1;
+ volatile uint16_t SMCR;
+ uint16_t _resvd2;
+ volatile uint16_t DIER;
+ uint16_t _resvd3;
+ volatile uint16_t SR;
+ uint16_t _resvd4;
+ volatile uint16_t EGR;
+ uint16_t _resvd5;
+ volatile uint16_t CCMR1;
+ uint16_t _resvd6;
+ volatile uint16_t CCMR2;
+ uint16_t _resvd7;
+ volatile uint16_t CCER;
+ uint16_t _resvd8;
+ volatile uint32_t CNT;
+ volatile uint16_t PSC;
+ uint16_t _resvd9;
+ volatile uint32_t ARR;
+ volatile uint16_t RCR;
+ uint16_t _resvd10;
+ volatile uint32_t CCR[4];
+ volatile uint16_t BDTR;
+ uint16_t _resvd11;
+ volatile uint16_t DCR;
+ uint16_t _resvd12;
+ volatile uint16_t DMAR;
+ uint16_t _resvd13;
+ volatile uint16_t OR;
+ uint16_t _resvd14;
+} TIM_TypeDef;
+
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
@@ -108,18 +155,6 @@
/* External declarations. */
/*===========================================================================*/
-/* Tricks required to make the TRUE/FALSE declaration inside the library
- compatible.*/
-#undef FALSE
-#undef TRUE
-#include "stm32f10x.h"
-#define FALSE 0
-#define TRUE (!FALSE)
-
-/* STM32 DMA and RCC helpers.*/
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/platforms/STM32F1xx/stm32f10x.h b/os/hal/platforms/STM32F1xx/stm32f10x.h
index 6697b9648..e8f413763 100644
--- a/os/hal/platforms/STM32F1xx/stm32f10x.h
+++ b/os/hal/platforms/STM32F1xx/stm32f10x.h
@@ -1198,6 +1198,8 @@ typedef struct
* @brief TIM
*/
+/* CHIBIOS FIX */
+#if 0
typedef struct
{
__IO uint16_t CR1;
@@ -1241,6 +1243,7 @@ typedef struct
__IO uint16_t DMAR;
uint16_t RESERVED19;
} TIM_TypeDef;
+#endif
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 11bdfedd6..71207efd5 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -1262,6 +1262,47 @@
/* Driver data structures and types. */
/*===========================================================================*/
+/**
+ * @brief STM32 TIM registers block.
+ * @note Removed from the ST headers and redefined because the non uniform
+ * declaration of the CCR registers among the various sub-families.
+ */
+typedef struct {
+ volatile uint16_t CR1;
+ uint16_t _resvd0;
+ volatile uint16_t CR2;
+ uint16_t _resvd1;
+ volatile uint16_t SMCR;
+ uint16_t _resvd2;
+ volatile uint16_t DIER;
+ uint16_t _resvd3;
+ volatile uint16_t SR;
+ uint16_t _resvd4;
+ volatile uint16_t EGR;
+ uint16_t _resvd5;
+ volatile uint16_t CCMR1;
+ uint16_t _resvd6;
+ volatile uint16_t CCMR2;
+ uint16_t _resvd7;
+ volatile uint16_t CCER;
+ uint16_t _resvd8;
+ volatile uint32_t CNT;
+ volatile uint16_t PSC;
+ uint16_t _resvd9;
+ volatile uint32_t ARR;
+ volatile uint16_t RCR;
+ uint16_t _resvd10;
+ volatile uint32_t CCR[4];
+ volatile uint16_t BDTR;
+ uint16_t _resvd11;
+ volatile uint16_t DCR;
+ uint16_t _resvd12;
+ volatile uint16_t DMAR;
+ uint16_t _resvd13;
+ volatile uint16_t OR;
+ uint16_t _resvd14;
+} TIM_TypeDef;
+
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32F4xx/stm32f4xx.h b/os/hal/platforms/STM32F4xx/stm32f4xx.h
index ccc1a3565..cd8ed7887 100644
--- a/os/hal/platforms/STM32F4xx/stm32f4xx.h
+++ b/os/hal/platforms/STM32F4xx/stm32f4xx.h
@@ -868,6 +868,8 @@ typedef struct
* @brief TIM
*/
+/* CHIBIOS FIX */
+#if 0
typedef struct
{
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
@@ -907,6 +909,7 @@ typedef struct
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
uint16_t RESERVED14; /*!< Reserved, 0x52 */
} TIM_TypeDef;
+#endif
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h
index 8d8f1b23b..d62176a16 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.h
+++ b/os/hal/platforms/STM32L1xx/hal_lld.h
@@ -37,13 +37,11 @@
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
-/* Tricks required to make the TRUE/FALSE declaration inside the library
- compatible.*/
-#undef FALSE
-#undef TRUE
#include "stm32l1xx.h"
-#define FALSE 0
-#define TRUE (!FALSE)
+
+/* STM32 DMA and RCC helpers.*/
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
/*===========================================================================*/
/* Driver constants. */
@@ -933,6 +931,47 @@
/* Driver data structures and types. */
/*===========================================================================*/
+/**
+ * @brief STM32 TIM registers block.
+ * @note Removed from the ST headers and redefined because the non uniform
+ * declaration of the CCR registers among the various sub-families.
+ */
+typedef struct {
+ volatile uint16_t CR1;
+ uint16_t _resvd0;
+ volatile uint16_t CR2;
+ uint16_t _resvd1;
+ volatile uint16_t SMCR;
+ uint16_t _resvd2;
+ volatile uint16_t DIER;
+ uint16_t _resvd3;
+ volatile uint16_t SR;
+ uint16_t _resvd4;
+ volatile uint16_t EGR;
+ uint16_t _resvd5;
+ volatile uint16_t CCMR1;
+ uint16_t _resvd6;
+ volatile uint16_t CCMR2;
+ uint16_t _resvd7;
+ volatile uint16_t CCER;
+ uint16_t _resvd8;
+ volatile uint32_t CNT;
+ volatile uint16_t PSC;
+ uint16_t _resvd9;
+ volatile uint32_t ARR;
+ volatile uint16_t RCR;
+ uint16_t _resvd10;
+ volatile uint32_t CCR[4];
+ volatile uint16_t BDTR;
+ uint16_t _resvd11;
+ volatile uint16_t DCR;
+ uint16_t _resvd12;
+ volatile uint16_t DMAR;
+ uint16_t _resvd13;
+ volatile uint16_t OR;
+ uint16_t _resvd14;
+} TIM_TypeDef;
+
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
@@ -941,10 +980,6 @@
/* External declarations. */
/*===========================================================================*/
-/* STM32 DMA and RCC helpers.*/
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h
index 32ddcb79d..5fadee5db 100644
--- a/os/hal/platforms/STM32L1xx/stm32l1xx.h
+++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h
@@ -615,6 +615,8 @@ typedef struct
* @brief TIM
*/
+/* CHIBIOS FIX */
+#if 0
typedef struct
{
__IO uint16_t CR1;
@@ -658,6 +660,7 @@ typedef struct
__IO uint16_t OR;
uint16_t RESERVED20;
} TIM_TypeDef;
+#endif
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 19:09:09 +0000