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-rw-r--r--os/hal/ports/STM32/LLD/ADCv1/adc_lld.c2
-rw-r--r--os/hal/ports/STM32/LLD/ADCv1/adc_lld.h4
-rw-r--r--os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c83
-rw-r--r--os/hal/ports/STM32/LLD/EXTIv1/notes.txt23
-rw-r--r--os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c60
-rw-r--r--os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h13
-rw-r--r--os/hal/ports/STM32/STM32F0xx/stm32_registry.h2
-rw-r--r--os/hal/ports/STM32/STM32F1xx/stm32_registry.h14
-rw-r--r--os/hal/ports/STM32/STM32F37x/stm32_registry.h8
-rw-r--r--os/hal/ports/STM32/STM32F4xx/stm32_registry.h8
-rw-r--r--os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c14
-rw-r--r--os/hal/ports/STM32/STM32L0xx/stm32_registry.h31
-rw-r--r--os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c10
-rw-r--r--os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h7
-rw-r--r--os/hal/ports/STM32/STM32L1xx/stm32_registry.h4
15 files changed, 206 insertions, 77 deletions
diff --git a/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c b/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c
index d8e70201a..bd73a315f 100644
--- a/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c
+++ b/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c
@@ -141,10 +141,12 @@ void adc_lld_init(void) {
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#if STM32_ADC1_IRQ_SHARED_WITH_EXTI == FALSE
/* The shared vector is initialized on driver initialization and never
disabled.*/
nvicEnableVector(12, STM32_ADC_ADC1_IRQ_PRIORITY);
#endif
+#endif
/* Calibration procedure.*/
rccEnableADC1(FALSE);
diff --git a/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h b/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h
index a561129e4..341866101 100644
--- a/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h
+++ b/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h
@@ -132,7 +132,7 @@
/**
* @brief ADC interrupt priority level setting.
*/
-#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#endif
@@ -168,10 +168,12 @@
#error "ADC driver activated but no ADC peripheral assigned"
#endif
+#if STM32_ADC1_IRQ_SHARED_WITH_EXTI == FALSE
#if STM32_ADC_USE_ADC1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1"
#endif
+#endif
#if STM32_ADC_USE_ADC1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
diff --git a/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c b/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c
index 314ca2899..4b649dbf2 100644
--- a/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c
+++ b/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c
@@ -74,17 +74,17 @@ void ext_lld_init(void) {
* @notapi
*/
void ext_lld_start(EXTDriver *extp) {
- unsigned i;
+ expchannel_t line;
if (extp->state == EXT_STOP)
ext_lld_exti_irq_enable();
/* Configuration of automatic channels.*/
- for (i = 0; i < EXT_MAX_CHANNELS; i++)
- if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
- ext_lld_channel_enable(extp, i);
+ for (line = 0; line < EXT_MAX_CHANNELS; line++)
+ if (extp->config->channels[line].mode & EXT_CH_MODE_AUTOSTART)
+ ext_lld_channel_enable(extp, line);
else
- ext_lld_channel_disable(extp, i);
+ ext_lld_channel_disable(extp, line);
}
/**
@@ -99,11 +99,12 @@ void ext_lld_stop(EXTDriver *extp) {
if (extp->state == EXT_ACTIVE)
ext_lld_exti_irq_disable();
- EXTI->EMR = 0;
- EXTI->IMR = 0;
- EXTI->PR = 0xFFFFFFFF;
+ EXTI->EMR = 0;
+ EXTI->IMR = STM32_EXTI_IMR_MASK;
+ EXTI->PR = ~STM32_EXTI_IMR_MASK;
#if STM32_EXTI_NUM_LINES > 32
- EXTI->PR2 = 0xFFFFFFFF;
+ EXTI->IMR2 = STM32_EXTI_IMR2_MASK;
+ EXTI->PR2 = ~STM32_EXTI_IMR2_MASK;
#endif
}
@@ -116,6 +117,7 @@ void ext_lld_stop(EXTDriver *extp) {
* @notapi
*/
void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
+ uint32_t cmask = (1 << (channel & 0x1F));
/* Setting the associated GPIO for external channels.*/
if (channel < 16) {
@@ -135,46 +137,56 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
#if STM32_EXTI_NUM_LINES > 32
if (channel < 32) {
#endif
+ /* Masked out lines must not be touched by this driver.*/
+ if ((cmask & STM32_EXTI_IMR_MASK) != 0U) {
+ return;
+ }
+
/* Programming edge registers.*/
if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
- EXTI->RTSR |= (1 << channel);
+ EXTI->RTSR |= cmask;
else
- EXTI->RTSR &= ~(1 << channel);
+ EXTI->RTSR &= ~cmask;
if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
- EXTI->FTSR |= (1 << channel);
+ EXTI->FTSR |= cmask;
else
- EXTI->FTSR &= ~(1 << channel);
+ EXTI->FTSR &= ~cmask;
/* Programming interrupt and event registers.*/
if (extp->config->channels[channel].cb != NULL) {
- EXTI->IMR |= (1 << channel);
- EXTI->EMR &= ~(1 << channel);
+ EXTI->IMR |= cmask;
+ EXTI->EMR &= ~cmask;
}
else {
- EXTI->EMR |= (1 << channel);
- EXTI->IMR &= ~(1 << channel);
+ EXTI->EMR |= cmask;
+ EXTI->IMR &= ~cmask;
}
#if STM32_EXTI_NUM_LINES > 32
}
else {
+ /* Masked out lines must not be touched by this driver.*/
+ if ((cmask & STM32_EXTI_IMR2_MASK) != 0U) {
+ return;
+ }
+
/* Programming edge registers.*/
if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
- EXTI->RTSR2 |= (1 << (32 - channel));
+ EXTI->RTSR2 |= cmask;
else
- EXTI->RTSR2 &= ~(1 << (32 - channel));
+ EXTI->RTSR2 &= ~cmask;
if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
- EXTI->FTSR2 |= (1 << (32 - channel));
+ EXTI->FTSR2 |= cmask;
else
- EXTI->FTSR2 &= ~(1 << (32 - channel));
+ EXTI->FTSR2 &= ~cmask;
/* Programming interrupt and event registers.*/
if (extp->config->channels[channel].cb != NULL) {
- EXTI->IMR2 |= (1 << (32 - channel));
- EXTI->EMR2 &= ~(1 << (32 - channel));
+ EXTI->IMR2 |= cmask;
+ EXTI->EMR2 &= ~cmask;
}
else {
- EXTI->EMR2 |= (1 << (32 - channel));
- EXTI->IMR2 &= ~(1 << (32 - channel));
+ EXTI->EMR2 |= cmask;
+ EXTI->IMR2 &= ~cmask;
}
}
#endif
@@ -189,25 +201,26 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
* @notapi
*/
void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
+ uint32_t cmask = (1 << (channel & 0x1F));
(void)extp;
#if STM32_EXTI_NUM_LINES > 32
if (channel < 32) {
#endif
- EXTI->IMR &= ~(1 << channel);
- EXTI->EMR &= ~(1 << channel);
- EXTI->RTSR &= ~(1 << channel);
- EXTI->FTSR &= ~(1 << channel);
- EXTI->PR = (1 << channel);
+ EXTI->IMR &= ~cmask;
+ EXTI->EMR &= ~cmask;
+ EXTI->RTSR &= ~cmask;
+ EXTI->FTSR &= ~cmask;
+ EXTI->PR = cmask;
#if STM32_EXTI_NUM_LINES > 32
}
else {
- EXTI->IMR2 &= ~(1 << (32 - channel));
- EXTI->EMR2 &= ~(1 << (32 - channel));
- EXTI->RTSR2 &= ~(1 << (32 - channel));
- EXTI->FTSR2 &= ~(1 << (32 - channel));
- EXTI->PR2 = (1 << (32 - channel));
+ EXTI->IMR2 &= ~cmask;
+ EXTI->EMR2 &= ~cmask;
+ EXTI->RTSR2 &= ~cmask;
+ EXTI->FTSR2 &= ~cmask;
+ EXTI->PR2 = cmask;
}
#endif
}
diff --git a/os/hal/ports/STM32/LLD/EXTIv1/notes.txt b/os/hal/ports/STM32/LLD/EXTIv1/notes.txt
new file mode 100644
index 000000000..10eda50d4
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/EXTIv1/notes.txt
@@ -0,0 +1,23 @@
+STM32 EXT driver implementation through EXTI unit.
+
+There are several kind of EXTI lines:
+
+1) GPIO lines. Always in range 0..15, always handled by the EXT driver.
+2) Configurable peripheral events not shared, always handled by the EXT driver.
+3) Configurable peripheral events shared with other, non EXTI, interrupts.
+ The EXTI driver declares the ISR and has to call the IRQ handler of the
+ other driver.
+4) Direct lines (1 in IMR register after reset). The EXTI driver never touches
+ the default configuration for direct lines and does not declare ISRs.
+5) Unused lines. The EXTI driver does not declare ISRs.
+
+The file registry must export:
+STM32_EXTI_NUM_LINES - Range of configurable lines, it can have holes of
+ unused or direct lines. Configurable line numbers go
+ from 0 to STM32_EXTI_NUM_LINES-1.
+STM32_EXTI_IMR_MASK - Direct lines and unused lines marked as 1 in this
+ mask, configurable lines marked as 0.
+STM32_EXTI_IMR2_MASK - Optional, for lines 32...63.
+
+ISRs are not declared inside the driver, each sub-family must have its own
+ext_lld_isr.h and ext_lld_isr.c files.
diff --git a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c
index be5d76a09..99fd15cf5 100644
--- a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c
+++ b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c
@@ -130,6 +130,7 @@ OSAL_IRQ_HANDLER(Vector5C) {
OSAL_IRQ_EPILOGUE();
}
+#if !defined(STM32F030) || defined(__DOXYGEN__)
/**
* @brief EXTI[16] interrupt handler (PVD).
*
@@ -144,21 +145,70 @@ OSAL_IRQ_HANDLER(Vector44) {
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if !defined(STM32_DISABLE_EXTI171920_HANDLER)
/**
- * @brief EXTI[17] interrupt handler (RTC).
+ * @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC).
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 17);
- EXTD1.config->channels[17].cb(&EXTD1, 17);
+ pr = EXTI->PR & EXTI->IMR & ((1 << 17) | (1 << 19) | (1 << 20));
+ EXTI->PR = pr;
+ if (pr & (1 << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+ if (pr & (1 << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+ if (pr & (1 << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
OSAL_IRQ_EPILOGUE();
}
+#endif
+#endif /* HAL_USE_EXT */
+
+#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__)
+#if !defined(STM32F030) || defined(__DOXYGEN__)
+#if !defined(STM32_DISABLE_EXTI2122_HANDLER)
+/**
+ * @brief EXTI[21],EXTI[22] interrupt handler (ADC, COMP).
+ * @note This handler is shared with the ADC so it is handled
+ * a bit differently.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+
+ OSAL_IRQ_PROLOGUE();
+
+#if HAL_USE_EXT
+ {
+ uint32_t pr;
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 21) | (1 << 22));
+ EXTI->PR = pr;
+ if (pr & (1 << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1 << 22))
+ EXTD1.config->channels[21].cb(&EXTD1, 22);
+ }
+#endif
+#if HAL_USE_ADC
+ adc_lld_serve_interrupt(&ADCD1);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+#endif /* !defined(STM32F030) */
+#endif /* HAL_USE_EXT || HAL_USE_ADC */
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver exported functions. */
@@ -176,8 +226,9 @@ void ext_lld_exti_irq_enable(void) {
nvicEnableVector(EXTI4_15_IRQn, STM32_EXT_EXTI4_15_IRQ_PRIORITY);
#if !defined(STM32F030)
nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(ADC1_COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
#endif
- nvicEnableVector(RTC_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+ nvicEnableVector(RTC_IRQn, STM32_EXT_EXTI17_20_IRQ_PRIORITY);
}
/**
@@ -192,6 +243,7 @@ void ext_lld_exti_irq_disable(void) {
nvicDisableVector(EXTI4_15_IRQn);
#if !defined(STM32F030)
nvicDisableVector(PVD_IRQn);
+ nvicDisableVector(ADC1_COMP_IRQn);
#endif
nvicDisableVector(RTC_IRQn);
}
diff --git a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h
index b9282e15d..4adc03597 100644
--- a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h
+++ b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h
@@ -68,10 +68,17 @@
#endif
/**
- * @brief EXTI17 interrupt priority level setting.
+ * @brief EXTI17,19,20 interrupt priority level setting.
*/
-#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
+#if !defined(STM32_EXT_EXTI17_20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI21,22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3
#endif
/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
index 7874cef34..a7abd8e25 100644
--- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
@@ -902,7 +902,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 20
-#define STM32_EXTI_IMR_MASK 0xFFF40000U
+#define STM32_EXTI_IMR_MASK 0xFFF50000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
index 5517505cf..8d04b3492 100644
--- a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
@@ -69,7 +69,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 18
-#define STM32_EXTI_IMR_MASK 0xFFFC0000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -233,7 +233,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 19
-#define STM32_EXTI_IMR_MASK 0xFFF80000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -405,7 +405,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 19
-#define STM32_EXTI_IMR_MASK 0xFFF80000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -550,7 +550,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 19
-#define STM32_EXTI_IMR_MASK 0xFFF80000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -714,7 +714,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 19
-#define STM32_EXTI_IMR_MASK 0xFFF80000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -914,7 +914,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 19
-#define STM32_EXTI_IMR_MASK 0xFFF80000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -1114,7 +1114,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 20
-#define STM32_EXTI_IMR_MASK 0xFFF00000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
diff --git a/os/hal/ports/STM32/STM32F37x/stm32_registry.h b/os/hal/ports/STM32/STM32F37x/stm32_registry.h
index 52676b5f7..43ffc9d63 100644
--- a/os/hal/ports/STM32/STM32F37x/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F37x/stm32_registry.h
@@ -73,8 +73,8 @@
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 29
-#define STM32_EXTI_IMR_MASK 0xE0000000U
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x1F800000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -278,8 +278,8 @@
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 29
-#define STM32_EXTI_IMR_MASK 0xE0000000U
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0x1F800000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
index e7a27f389..9e34b7ce3 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -110,7 +110,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR_MASK 0xFF800000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -408,7 +408,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR_MASK 0xFF800000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -681,7 +681,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR_MASK 0xFF800000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -902,7 +902,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR_MASK 0xFF800000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
diff --git a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c
index 36731f9bb..ba94cc74c 100644
--- a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c
+++ b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c
@@ -48,6 +48,7 @@
/* Driver interrupt handlers. */
/*===========================================================================*/
+#if !defined(STM32_DISABLE_EXTI01_HANDLER)
/**
* @brief EXTI[0]...EXTI[1] interrupt handler.
*
@@ -67,7 +68,9 @@ OSAL_IRQ_HANDLER(STM32_EXTI_LINE01_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if !defined(STM32_DISABLE_EXTI23_HANDLER)
/**
* @brief EXTI[2]...EXTI[3] interrupt handler.
*
@@ -87,7 +90,9 @@ OSAL_IRQ_HANDLER(STM32_EXTI_LINE23_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if !defined(STM32_DISABLE_EXTI4_15_HANDLER)
/**
* @brief EXTI[4]...EXTI[15] interrupt handler.
*
@@ -129,7 +134,9 @@ OSAL_IRQ_HANDLER(STM32_EXTI_LINE4_15_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if !defined(STM32_DISABLE_EXTI16_HANDLER)
/**
* @brief EXTI[16] interrupt handler (PVD).
*
@@ -147,7 +154,9 @@ OSAL_IRQ_HANDLER(STM32_EXTI_LINE16_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
+#endif
+#if !defined(STM32_DISABLE_EXTI171920_HANDLER)
/**
* @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC, CSS).
*
@@ -169,11 +178,13 @@ OSAL_IRQ_HANDLER(STM32_EXTI_LINE171920_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
+#endif
#endif /* HAL_USE_EXT */
#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__)
+#if !defined(STM32_DISABLE_EXTI2122_HANDLER)
/**
- * @brief EXTI[20],EXTI[21] interrupt handler (ADC, COMP).
+ * @brief EXTI[21],EXTI[22] interrupt handler (ADC, COMP).
* @note This handler is shared with the ADC so it is handled
* a bit differently.
*
@@ -201,6 +212,7 @@ OSAL_IRQ_HANDLER(STM32_EXTI_LINE2122_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
+#endif
#endif /* HAL_USE_EXT || HAL_USE_ADC */
#if HAL_USE_EXT || defined(__DOXYGEN__)
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h
index 7ea436f9c..bbc26e382 100644
--- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h
@@ -83,6 +83,20 @@
#define STM32_EXTI_NUM_LINES 23
#define STM32_EXTI_IMR_MASK 0xFF840000U
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
+
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@@ -151,21 +165,6 @@
#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR_MASK 0xFF840000U
-
-#define STM32_EXTI_LINE01_HANDLER Vector54
-#define STM32_EXTI_LINE23_HANDLER Vector58
-#define STM32_EXTI_LINE4_15_HANDLER Vector5C
-#define STM32_EXTI_LINE171920_HANDLER Vector48
-#define STM32_EXTI_LINE2122_HANDLER Vector70
-
-#define STM32_EXTI_LINE01_NUMBER 5
-#define STM32_EXTI_LINE23_NUMBER 6
-#define STM32_EXTI_LINE4_15_NUMBER 7
-#define STM32_EXTI_LINE171920_NUMBER 2
-#define STM32_EXTI_LINE2122_NUMBER 12
-
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
@@ -309,12 +308,14 @@
#define STM32_EXTI_LINE01_HANDLER Vector54
#define STM32_EXTI_LINE23_HANDLER Vector58
#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
#define STM32_EXTI_LINE171920_HANDLER Vector48
#define STM32_EXTI_LINE2122_HANDLER Vector70
#define STM32_EXTI_LINE01_NUMBER 5
#define STM32_EXTI_LINE23_NUMBER 6
#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
#define STM32_EXTI_LINE171920_NUMBER 2
#define STM32_EXTI_LINE2122_NUMBER 12
diff --git a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
index 148883fcf..727d15891 100644
--- a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
+++ b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
@@ -305,7 +305,11 @@ OSAL_IRQ_HANDLER(Vector98) {
*
* @isr
*/
+#if defined(STM32L1XX_MDP) || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(Vector114) {
+#else
OSAL_IRQ_HANDLER(Vector120) {
+#endif
uint32_t pr;
OSAL_IRQ_PROLOGUE();
@@ -342,6 +346,9 @@ void ext_lld_exti_irq_enable(void) {
nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+#if STM32_EXTI_NUM_LINES > 23
+ nvicEnableVector(COMP_ACQ_IRQn, STM32_EXT_EXTI23_IRQ_PRIORITY);
+#endif
}
/**
@@ -364,6 +371,9 @@ void ext_lld_exti_irq_disable(void) {
nvicDisableVector(TAMPER_STAMP_IRQn);
nvicDisableVector(RTC_WKUP_IRQn);
nvicDisableVector(COMP_IRQn);
+#if STM32_EXTI_NUM_LINES > 23
+ nvicDisableVector(COMP_ACQ_IRQn);
+#endif
}
#endif /* HAL_USE_EXT */
diff --git a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h
index 38683a51c..1554ae285 100644
--- a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h
+++ b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h
@@ -129,6 +129,13 @@
#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
#endif
+
+/**
+ * @brief EXTI23 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI23_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI23_IRQ_PRIORITY 6
+#endif
/** @} */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
index dd84ad6b6..5dc7d21c7 100644
--- a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
@@ -66,7 +66,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR_MASK 0xFF800000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -247,7 +247,7 @@
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 24
-#define STM32_EXTI_IMR_MASK 0xFF000000U
+#define STM32_EXTI_IMR_MASK 0x00000000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 21:47:35 +0000