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-rw-r--r--os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c69
-rw-r--r--os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h30
-rw-r--r--os/hal/ports/STM32/STM32H7xx/platform.mk1
-rw-r--r--os/hal/ports/STM32/STM32H7xx/stm32_dmamux.h4
-rw-r--r--os/hal/ports/STM32/STM32H7xx/stm32_rcc.h6
-rw-r--r--os/hal/ports/STM32/STM32H7xx/stm32_registry.h4
6 files changed, 72 insertions, 42 deletions
diff --git a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
index 0b2f5d2af..67758ff73 100644
--- a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
+++ b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
@@ -88,10 +88,10 @@ static const dacparams_t dma1_ch1_params = {
.regshift = 0U,
.regmask = 0xFFFF0000U,
#if STM32_DMA_SUPPORTS_DMAMUX
- .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_CHANNEL),
+ .dmachannel = STM32_DAC_DAC1_CH1_DMA_CHANNEL,
.peripheral = STM32_DMAMUX1_DAC1_CH1,
#else
- .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
+ .dmachannel = STM32_DAC_DAC1_CH1_DMA_STREAM,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
@@ -109,10 +109,10 @@ static const dacparams_t dma1_ch2_params = {
.regshift = 16U,
.regmask = 0x0000FFFFU,
#if STM32_DMA_SUPPORTS_DMAMUX
- .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_CHANNEL),
+ .dmachannel = STM32_DAC_DAC1_CH2_DMA_CHANNEL,
.peripheral = STM32_DMAMUX1_DAC1_CH2,
#else
- .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
+ .dmachannel = STM32_DAC_DAC1_CH2_DMA_STREAM,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
@@ -130,10 +130,10 @@ static const dacparams_t dma2_ch1_params = {
.regshift = 0U,
.regmask = 0xFFFF0000U,
#if STM32_DMA_SUPPORTS_DMAMUX
- .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_CHANNEL),
+ .dmachannel = STM32_DAC_DAC2_CH1_DMA_CHANNEL,
.peripheral = STM32_DMAMUX1_DAC2_CH1,
#else
- .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM),
+ .dmachannel = STM32_DAC_DAC2_CH1_DMA_STREAM,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
@@ -151,10 +151,10 @@ static const dacparams_t dma1_ch2_params = {
.regshift = 16U,
.regmask = 0x0000FFFFU,
#if STM32_DMA_SUPPORTS_DMAMUX
- .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_CHANNEL),
+ .dmachannel = STM32_DAC_DAC2_CH2_DMA_CHANNEL,
.peripheral = STM32_DMAMUX1_DAC2_CH2,
#else
- .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM),
+ .dmachannel = STM32_DAC_DAC2_CH2_DMA_STREAM,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
@@ -211,21 +211,25 @@ void dac_lld_init(void) {
#if STM32_DAC_USE_DAC1_CH1
dacObjectInit(&DACD1);
DACD1.params = &dma1_ch1_params;
+ DACD1.dma = NULL;
#endif
#if STM32_DAC_USE_DAC1_CH2
dacObjectInit(&DACD2);
DACD2.params = &dma1_ch2_params;
+ DACD2.dma = NULL;
#endif
#if STM32_DAC_USE_DAC2_CH1
dacObjectInit(&DACD3);
DACD3.params = &dma2_ch1_params;
+ DACD3.dma = NULL;
#endif
#if STM32_DAC_USE_DAC2_CH2
dacObjectInit(&DACD4);
DACD4.params = &dma2_ch2_params;
+ DACD4.dma = NULL;
#endif
}
@@ -433,12 +437,13 @@ void dac_lld_start_conversion(DACDriver *dacp) {
n = dacp->depth * dacp->grpp->num_channels;
/* Allocating the DMA channel.*/
- bool b = dmaStreamAllocate(dacp->params->dma, dacp->params->dmairqprio,
- (stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
- (void *)dacp);
- osalDbgAssert(!b, "stream already allocated");
+ dacp->dma = dmaStreamAllocI(dacp->params->dmachannel,
+ dacp->params->dmairqprio,
+ (stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
+ (void *)dacp);
+ osalDbgAssert(dacp->dma != NULL, "unable to allocate stream");
#if STM32_DMA_SUPPORTS_DMAMUX
- dmaSetRequestSource(dacp->params->dma, dacp->params->peripheral);
+ dmaSetRequestSource(dacp->dma, dacp->params->peripheral);
#endif
/* DMA settings depend on the chosen DAC mode.*/
@@ -447,24 +452,24 @@ void dac_lld_start_conversion(DACDriver *dacp) {
case DAC_DHRM_12BIT_RIGHT:
osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
- dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12R1 +
- dacp->params->dataoffset);
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12R1 +
+ dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_12BIT_LEFT:
osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
- dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12L1 +
- dacp->params->dataoffset);
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12L1 +
+ dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_8BIT_RIGHT:
osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
- dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR8R1 +
- dacp->params->dataoffset);
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8R1 +
+ dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
@@ -476,7 +481,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
case DAC_DHRM_12BIT_RIGHT_DUAL:
osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
- dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12RD);
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12RD);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
n /= 2;
@@ -484,7 +489,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
case DAC_DHRM_12BIT_LEFT_DUAL:
osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
- dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12LD);
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12LD);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
n /= 2;
@@ -492,7 +497,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
case DAC_DHRM_8BIT_RIGHT_DUAL:
osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
- dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR8RD);
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8RD);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
n /= 2;
@@ -503,12 +508,12 @@ void dac_lld_start_conversion(DACDriver *dacp) {
return;
}
- dmaStreamSetMemory0(dacp->params->dma, dacp->samples);
- dmaStreamSetTransactionSize(dacp->params->dma, n);
- dmaStreamSetMode(dacp->params->dma, dmamode |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE);
- dmaStreamEnable(dacp->params->dma);
+ dmaStreamSetMemory0(dacp->dma, dacp->samples);
+ dmaStreamSetTransactionSize(dacp->dma, n);
+ dmaStreamSetMode(dacp->dma, dmamode |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
+ STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE);
+ dmaStreamEnable(dacp->dma);
/* DAC configuration.*/
#if STM32_DAC_DUAL_MODE == FALSE
@@ -536,8 +541,9 @@ void dac_lld_start_conversion(DACDriver *dacp) {
void dac_lld_stop_conversion(DACDriver *dacp) {
/* DMA channel disabled and released.*/
- dmaStreamDisable(dacp->params->dma);
- dmaStreamRelease(dacp->params->dma);
+ dmaStreamDisable(dacp->dma);
+ dmaStreamRelease(dacp->dma);
+ dacp->dma = NULL;
#if STM32_DAC_DUAL_MODE == FALSE
dacp->params->dac->CR &= dacp->params->regmask;
@@ -546,7 +552,8 @@ void dac_lld_stop_conversion(DACDriver *dacp) {
if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
(dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
(dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
- dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) | DAC_CR_EN1 | dacp->config->cr;
+ dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) |
+ DAC_CR_EN1 | dacp->config->cr;
}
else {
dacp->params->dac->CR = DAC_CR_EN1 | dacp->config->cr;
diff --git a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
index d66a8b0e7..e84a250e9 100644
--- a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
+++ b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
@@ -177,6 +177,26 @@
#error "DAC driver activated but no DAC peripheral assigned"
#endif
+#if STM32_DAC_USE_DAC1_CH1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to DAC1 CH1"
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to DAC1 CH2"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to DAC2 CH1"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to DAC2 CH2"
+#endif
+
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
@@ -312,9 +332,9 @@ typedef struct {
*/
uint32_t regmask;
/**
- * @brief Associated DMA.
+ * @brief Associated DMA channel.
*/
- const stm32_dma_stream_t *dma;
+ uint32_t dmachannel;
/**
* @brief Mode bits for the DMA.
*/
@@ -364,7 +384,10 @@ typedef enum {
*/
#define dac_lld_driver_fields \
/* DAC channel parameters.*/ \
- const dacparams_t *params
+ const dacparams_t *params; \
+ /* Associated DMA.*/ \
+ const stm32_dma_stream_t *dma
+
/**
* @brief Low level fields of the DAC configuration structure.
@@ -376,7 +399,6 @@ typedef enum {
dacdhrmode_t datamode; \
/* DAC control register.*/ \
uint16_t cr
-
/**
* @brief Low level fields of the DAC group configuration structure.
*/
diff --git a/os/hal/ports/STM32/STM32H7xx/platform.mk b/os/hal/ports/STM32/STM32H7xx/platform.mk
index 890b8999a..d5b700105 100644
--- a/os/hal/ports/STM32/STM32H7xx/platform.mk
+++ b/os/hal/ports/STM32/STM32H7xx/platform.mk
@@ -24,6 +24,7 @@ endif
include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv4/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/BDMAv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv3/driver.mk
diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_dmamux.h b/os/hal/ports/STM32/STM32H7xx/stm32_dmamux.h
index 642aec210..2f173cbc9 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_dmamux.h
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_dmamux.h
@@ -99,8 +99,8 @@
#define STM32_DMAMUX1_UART4_TX 64
#define STM32_DMAMUX1_UART5_RX 65
#define STM32_DMAMUX1_UART5_TX 66
-#define STM32_DMAMUX1_DAC1 67
-#define STM32_DMAMUX1_DAC2 68
+#define STM32_DMAMUX1_DAC1_CH1 67 /* Renamed to L4 name.*/
+#define STM32_DMAMUX1_DAC1_CH2 68 /* Renamed to L4 name.*/
#define STM32_DMAMUX1_TIM6_UP 69
#define STM32_DMAMUX1_TIM7_UP 70
#define STM32_DMAMUX1_USART6_RX 71
diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
index c5d059353..d5a1c6de7 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
@@ -500,21 +500,21 @@
*
* @api
*/
-#define rccEnableDAC1(lp) rccEnableAPB1L(RCC_APB1LENR_DACEN, lp)
+#define rccEnableDAC1(lp) rccEnableAPB1L(RCC_APB1LENR_DAC12EN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @api
*/
-#define rccDisableDAC1() rccDisableAPB1L(RCC_APB1LENR_DACEN)
+#define rccDisableDAC1() rccDisableAPB1L(RCC_APB1LENR_DAC12EN)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
-#define rccResetDAC1() rccResetAPB1L(RCC_APB1LRSTR_DACRST)
+#define rccResetDAC1() rccResetAPB1L(RCC_APB1LRSTR_DAC12RST)
/** @} */
/**
diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
index 96ed7b079..dcaea0487 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
@@ -63,8 +63,8 @@
#define STM32_HAS_CAN3 FALSE
/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_HAS_DAC1_CH2 TRUE
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 18:33:08 +0000