diff options
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/STM32/SPIv1/spi_lld.c | 1 | ||||
| -rw-r--r-- | os/hal/ports/STM32/USARTv1/uart_lld.c | 1 | ||||
| -rw-r--r-- | os/hal/ports/STM32F37x/adc_lld.h | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32F37x/hal_lld.h | 35 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/adc_lld.c | 20 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/adc_lld.h | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/ext_lld_isr.c | 118 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/hal_lld.c | 12 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/hal_lld.h | 249 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/platform.mk | 47 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/stm32_dma.c | 59 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/stm32_dma.h | 8 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/stm32_registry.h | 175 |
13 files changed, 300 insertions, 429 deletions
diff --git a/os/hal/ports/STM32/SPIv1/spi_lld.c b/os/hal/ports/STM32/SPIv1/spi_lld.c index 74d21273a..2c8231086 100644 --- a/os/hal/ports/STM32/SPIv1/spi_lld.c +++ b/os/hal/ports/STM32/SPIv1/spi_lld.c @@ -22,7 +22,6 @@ * @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_SPI || defined(__DOXYGEN__)
diff --git a/os/hal/ports/STM32/USARTv1/uart_lld.c b/os/hal/ports/STM32/USARTv1/uart_lld.c index d77d9bd98..8f1bcfb13 100644 --- a/os/hal/ports/STM32/USARTv1/uart_lld.c +++ b/os/hal/ports/STM32/USARTv1/uart_lld.c @@ -22,7 +22,6 @@ * @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_UART || defined(__DOXYGEN__)
diff --git a/os/hal/ports/STM32F37x/adc_lld.h b/os/hal/ports/STM32F37x/adc_lld.h index 2258952b1..db7ae39ec 100644 --- a/os/hal/ports/STM32F37x/adc_lld.h +++ b/os/hal/ports/STM32F37x/adc_lld.h @@ -397,7 +397,7 @@ typedef struct { /**
* @brief Enables the circular buffer mode for the group.
*/
- bool_t circular;
+ bool circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
diff --git a/os/hal/ports/STM32F37x/hal_lld.h b/os/hal/ports/STM32F37x/hal_lld.h index 2d7a0dac1..763e70da0 100644 --- a/os/hal/ports/STM32F37x/hal_lld.h +++ b/os/hal/ports/STM32F37x/hal_lld.h @@ -965,48 +965,15 @@ /* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() DWT_CYCCNT
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() STM32_HCLK
-
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-/* STM32 ISR, DMA and RCC helpers.*/
+/* Various helpers.*/
#include "nvic.h"
#include "stm32_isr.h"
#include "stm32_dma.h"
diff --git a/os/hal/ports/STM32L1xx/adc_lld.c b/os/hal/ports/STM32L1xx/adc_lld.c index 5e6ec80a2..ab4b7cd1a 100644 --- a/os/hal/ports/STM32L1xx/adc_lld.c +++ b/os/hal/ports/STM32L1xx/adc_lld.c @@ -22,7 +22,6 @@ * @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_ADC || defined(__DOXYGEN__)
@@ -88,10 +87,10 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { *
* @isr
*/
-CH_IRQ_HANDLER(ADC1_IRQHandler) {
+OSAL_IRQ_HANDLER(ADC1_IRQHandler) {
uint32_t sr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
sr = ADC1->SR;
ADC1->SR = 0;
@@ -105,7 +104,7 @@ CH_IRQ_HANDLER(ADC1_IRQHandler) { }
/* TODO: Add here analog watchdog handling.*/
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
#endif
@@ -134,7 +133,7 @@ void adc_lld_init(void) { /* The shared vector is initialized on driver initialization and never
disabled.*/
- nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
+ nvicEnableVector(ADC1_IRQn, STM32_ADC_IRQ_PRIORITY);
}
/**
@@ -150,12 +149,11 @@ void adc_lld_start(ADCDriver *adcp) { if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
- bool_t b;
- b = dmaStreamAllocate(adcp->dmastp,
- STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
- (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
- (void *)adcp);
- chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
+ bool b = dmaStreamAllocate(adcp->dmastp,
+ STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+ (void *)adcp);
+ osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(FALSE);
}
diff --git a/os/hal/ports/STM32L1xx/adc_lld.h b/os/hal/ports/STM32L1xx/adc_lld.h index 2ac857c16..6d11ea93c 100644 --- a/os/hal/ports/STM32L1xx/adc_lld.h +++ b/os/hal/ports/STM32L1xx/adc_lld.h @@ -235,7 +235,7 @@ typedef struct { /**
* @brief Enables the circular buffer mode for the group.
*/
- bool_t circular;
+ bool circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
diff --git a/os/hal/ports/STM32L1xx/ext_lld_isr.c b/os/hal/ports/STM32L1xx/ext_lld_isr.c index ea9259a69..fda41f1ac 100644 --- a/os/hal/ports/STM32L1xx/ext_lld_isr.c +++ b/os/hal/ports/STM32L1xx/ext_lld_isr.c @@ -22,7 +22,6 @@ * @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
@@ -54,14 +53,14 @@ *
* @isr
*/
-CH_IRQ_HANDLER(EXTI0_IRQHandler) {
+OSAL_IRQ_HANDLER(EXTI0_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 0);
EXTD1.config->channels[0].cb(&EXTD1, 0);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -69,14 +68,14 @@ CH_IRQ_HANDLER(EXTI0_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(EXTI1_IRQHandler) {
+OSAL_IRQ_HANDLER(EXTI1_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 1);
EXTD1.config->channels[1].cb(&EXTD1, 1);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -84,14 +83,14 @@ CH_IRQ_HANDLER(EXTI1_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(EXTI2_IRQHandler) {
+OSAL_IRQ_HANDLER(EXTI2_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 2);
EXTD1.config->channels[2].cb(&EXTD1, 2);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -99,14 +98,14 @@ CH_IRQ_HANDLER(EXTI2_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(EXTI3_IRQHandler) {
+OSAL_IRQ_HANDLER(EXTI3_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 3);
EXTD1.config->channels[3].cb(&EXTD1, 3);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -114,14 +113,14 @@ CH_IRQ_HANDLER(EXTI3_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(EXTI4_IRQHandler) {
+OSAL_IRQ_HANDLER(EXTI4_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 4);
EXTD1.config->channels[4].cb(&EXTD1, 4);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -129,10 +128,10 @@ CH_IRQ_HANDLER(EXTI4_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
+OSAL_IRQ_HANDLER(EXTI9_5_IRQHandler) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
EXTI->PR = pr;
@@ -147,7 +146,7 @@ CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -155,10 +154,10 @@ CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
+OSAL_IRQ_HANDLER(EXTI15_10_IRQHandler) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
(1 << 15));
@@ -176,7 +175,7 @@ CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -184,14 +183,14 @@ CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(PVD_IRQHandler) {
+OSAL_IRQ_HANDLER(PVD_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -199,28 +198,28 @@ CH_IRQ_HANDLER(PVD_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
+OSAL_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
* @brief EXTI[18] interrupt handler (USB_FS_WKUP).
*
* @isr
*/
-CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 18);
EXTD1.config->channels[18].cb(&EXTD1, 18);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -228,14 +227,14 @@ CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
+OSAL_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 19);
EXTD1.config->channels[19].cb(&EXTD1, 19);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -243,14 +242,14 @@ CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
+OSAL_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
EXTI->PR = (1 << 20);
EXTD1.config->channels[20].cb(&EXTD1, 20);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -258,10 +257,10 @@ CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(COMP_IRQHandler) {
+OSAL_IRQ_HANDLER(COMP_IRQHandler) {
uint32_t pr;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 21) | (1 << 22));
EXTI->PR = pr;
@@ -270,7 +269,7 @@ CH_IRQ_HANDLER(COMP_IRQHandler) { if (pr & (1 << 22))
EXTD1.config->channels[22].cb(&EXTD1, 22);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
@@ -284,32 +283,19 @@ CH_IRQ_HANDLER(COMP_IRQHandler) { */
void ext_lld_exti_irq_enable(void) {
- nvicEnableVector(EXTI0_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
- nvicEnableVector(EXTI1_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
- nvicEnableVector(EXTI2_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
- nvicEnableVector(EXTI3_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
- nvicEnableVector(EXTI4_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
- nvicEnableVector(EXTI9_5_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
- nvicEnableVector(EXTI15_10_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
- nvicEnableVector(PVD_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
- nvicEnableVector(RTC_Alarm_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
- nvicEnableVector(USB_FS_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
- nvicEnableVector(TAMPER_STAMP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
- nvicEnableVector(RTC_WKUP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
- nvicEnableVector(COMP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_IRQ_PRIORITY));
+ nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+ nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+ nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+ nvicEnableVector(USB_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+ nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+ nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+ nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
}
/**
diff --git a/os/hal/ports/STM32L1xx/hal_lld.c b/os/hal/ports/STM32L1xx/hal_lld.c index 529099e6a..056a8fc88 100644 --- a/os/hal/ports/STM32L1xx/hal_lld.c +++ b/os/hal/ports/STM32L1xx/hal_lld.c @@ -24,7 +24,6 @@ /* TODO: LSEBYP like in F3.*/
-#include "ch.h"
#include "hal.h"
/*===========================================================================*/
@@ -98,17 +97,6 @@ void hal_lld_init(void) { rccResetAPB1(~RCC_APB1RSTR_PWRRST);
rccResetAPB2(~0);
- /* SysTick initialization using the system clock.*/
- SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk |
- SysTick_CTRL_TICKINT_Msk;
-
- /* DWT cycle counter enable.*/
- SCS_DEMCR |= SCS_DEMCR_TRCENA;
- DWT_CTRL |= DWT_CTRL_CYCCNTENA;
-
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
diff --git a/os/hal/ports/STM32L1xx/hal_lld.h b/os/hal/ports/STM32L1xx/hal_lld.h index 3e8692e93..dca4b5966 100644 --- a/os/hal/ports/STM32L1xx/hal_lld.h +++ b/os/hal/ports/STM32L1xx/hal_lld.h @@ -35,6 +35,7 @@ #define _HAL_LLD_H_
#include "stm32.h"
+#include "stm32_registry.h"
/*===========================================================================*/
/* Driver constants. */
@@ -167,218 +168,6 @@ /** @} */
/*===========================================================================*/
-/* Platform capabilities. */
-/*===========================================================================*/
-
-/**
- * @name STM32L1xx capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1 TRUE
-#define STM32_HAS_ADC2 FALSE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 FALSE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_CAN_MAX_FILTERS 0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 23
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOI FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN 0x00000000
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN 0x00000000
-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_I2C3 FALSE
-#define STM32_I2C3_RX_DMA_MSK 0
-#define STM32_I2C3_RX_DMA_CHN 0x00000000
-#define STM32_I2C3_TX_DMA_MSK 0
-#define STM32_I2C3_TX_DMA_CHN 0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#define STM32_RTC_IS_CALENDAR TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN 0x00000000
-#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 FALSE
-#define STM32_SPI3_RX_DMA_MSK 0
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK 0
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1 FALSE
-#define STM32_HAS_TIM2 TRUE
-#define STM32_HAS_TIM3 TRUE
-#define STM32_HAS_TIM4 TRUE
-#define STM32_HAS_TIM5 FALSE
-#define STM32_HAS_TIM6 TRUE
-#define STM32_HAS_TIM7 TRUE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM9 TRUE
-#define STM32_HAS_TIM10 TRUE
-#define STM32_HAS_TIM11 TRUE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4 FALSE
-#define STM32_UART4_RX_DMA_MSK 0
-#define STM32_UART4_RX_DMA_CHN 0x00000000
-#define STM32_UART4_TX_DMA_MSK 0
-#define STM32_UART4_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART5 FALSE
-#define STM32_UART5_RX_DMA_MSK 0
-#define STM32_UART5_RX_DMA_CHN 0x00000000
-#define STM32_UART5_TX_DMA_MSK 0
-#define STM32_UART5_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART6 FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB TRUE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-/** @} */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names. */
-/*===========================================================================*/
-
-/**
- * @name IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
-#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
- detect. */
-#define TAMPER_STAMP_IRQHandler Vector48 /**< Tamper and Time Stamp
- through EXTI. */
-#define RTC_WKUP_IRQHandler Vector4C /**< RTC Wakeup Timer through
- EXTI. */
-#define FLASH_IRQHandler Vector50 /**< Flash. */
-#define RCC_IRQHandler Vector54 /**< RCC. */
-#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
-#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
-#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
-#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
-#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
-#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */
-#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */
-#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */
-#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */
-#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */
-#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
-#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
-#define ADC1_IRQHandler Vector88 /**< ADC1. */
-#define USB_HP_IRQHandler Vector8C /**< USB High Priority. */
-#define USB_LP_IRQHandler Vector90 /**< USB Low Priority. */
-#define DAC_IRQHandler Vector94 /**< DAC. */
-#define COMP_IRQHandler Vector98 /**< Comparator through EXTI. */
-#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
-#define TIM9_IRQHandler VectorA0 /**< TIM9. */
-#define TIM10_IRQHandler VectorA4 /**< TIM10. */
-#define TIM11_IRQHandler VectorA8 /**< TIM11. */
-#define LCD_IRQHandler VectorAC /**< LCD. */
-#define TIM2_IRQHandler VectorB0 /**< TIM2. */
-#define TIM3_IRQHandler VectorB4 /**< TIM3. */
-#define TIM4_IRQHandler VectorB8 /**< TIM4. */
-#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
-#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
-#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
-#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */
-#define SPI1_IRQHandler VectorCC /**< SPI1. */
-#define SPI2_IRQHandler VectorD0 /**< SPI2. */
-#define USART1_IRQHandler VectorD4 /**< USART1. */
-#define USART2_IRQHandler VectorD8 /**< USART2. */
-#define USART3_IRQHandler VectorDC /**< USART3. */
-#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
-#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */
-#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */
-#define TIM6_IRQHandler VectorEC /**< TIM6. */
-#define TIM7_IRQHandler VectorF0 /**< TIM7. */
-/** @} */
-
-/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -1009,48 +798,16 @@ /* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() DWT_CYCCNT
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() STM32_HCLK
-
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
-/* STM32 ISR, DMA and RCC helpers.*/
+/* Various helpers.*/
+#include "nvic.h"
#include "stm32_isr.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"
diff --git a/os/hal/ports/STM32L1xx/platform.mk b/os/hal/ports/STM32L1xx/platform.mk index 4678792a5..4104e3369 100644 --- a/os/hal/ports/STM32L1xx/platform.mk +++ b/os/hal/ports/STM32L1xx/platform.mk @@ -1,25 +1,28 @@ # List of all the STM32L1xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
- ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32L1xx/ext_lld_isr.c \
- ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS}/os/hal/ports/STM32L1xx/stm32_dma.c \
+ ${CHIBIOS}/os/hal/ports/STM32L1xx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32L1xx/adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32L1xx/ext_lld_isr.c \
+ ${CHIBIOS}/os/hal/ports/STM32/ext_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/GPIOv2/pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/I2Cv1/i2c_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/SPIv1/spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/TIMv1/gpt_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/TIMv1/icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/TIMv1/pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/TIMv1/st_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/USARTv1/serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/USARTv1/uart_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/USBv1/usb_lld.c
# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32L1xx \
- ${CHIBIOS}/os/hal/platforms/STM32 \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
- ${CHIBIOS}/os/hal/platforms/STM32/USBv1
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS}/os/hal/ports/STM32L1xx \
+ ${CHIBIOS}/os/hal/ports/STM32 \
+ ${CHIBIOS}/os/hal/ports/STM32/GPIOv2 \
+ ${CHIBIOS}/os/hal/ports/STM32/I2Cv1 \
+ ${CHIBIOS}/os/hal/ports/STM32/SPIv1 \
+ ${CHIBIOS}/os/hal/ports/STM32/TIMv1 \
+ ${CHIBIOS}/os/hal/ports/STM32/USARTv1 \
+ ${CHIBIOS}/os/hal/ports/STM32/USBv1
diff --git a/os/hal/ports/STM32L1xx/stm32_dma.c b/os/hal/ports/STM32L1xx/stm32_dma.c index 31b475589..f277fab0d 100644 --- a/os/hal/ports/STM32L1xx/stm32_dma.c +++ b/os/hal/ports/STM32L1xx/stm32_dma.c @@ -29,7 +29,6 @@ * @{
*/
-#include "ch.h"
#include "hal.h"
/* The following macro is only defined if some driver requiring DMA services
@@ -111,17 +110,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; *
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
+OSAL_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[0].dma_func)
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -129,17 +128,17 @@ CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
+OSAL_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
if (dma_isr_redir[1].dma_func)
dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -147,17 +146,17 @@ CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
+OSAL_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
if (dma_isr_redir[2].dma_func)
dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -165,17 +164,17 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
+OSAL_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
if (dma_isr_redir[3].dma_func)
dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -183,17 +182,17 @@ CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
+OSAL_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[4].dma_func)
dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -201,17 +200,17 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
+OSAL_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
if (dma_isr_redir[5].dma_func)
dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/**
@@ -219,17 +218,17 @@ CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { *
* @isr
*/
-CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
+OSAL_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
uint32_t flags;
- CH_IRQ_PROLOGUE();
+ OSAL_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
if (dma_isr_redir[6].dma_func)
dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
- CH_IRQ_EPILOGUE();
+ OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
@@ -276,12 +275,12 @@ void dmaInit(void) { *
* @special
*/
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param) {
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+ uint32_t priority,
+ stm32_dmaisr_t func,
+ void *param) {
- chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
+ osalDbgCheck(dmastp != NULL);
/* Checks if the stream is already taken.*/
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
@@ -322,11 +321,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, */
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
- chDbgCheck(dmastp != NULL, "dmaStreamRelease");
+ osalDbgCheck(dmastp != NULL);
/* Check if the streams is not taken.*/
- chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
- "dmaStreamRelease(), #1", "not allocated");
+ osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+ "not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector);
diff --git a/os/hal/ports/STM32L1xx/stm32_dma.h b/os/hal/ports/STM32L1xx/stm32_dma.h index 2e3225ce9..3af798d0b 100644 --- a/os/hal/ports/STM32L1xx/stm32_dma.h +++ b/os/hal/ports/STM32L1xx/stm32_dma.h @@ -382,10 +382,10 @@ extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; extern "C" {
#endif
void dmaInit(void);
- bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param);
+ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+ uint32_t priority,
+ stm32_dmaisr_t func,
+ void *param);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
#ifdef __cplusplus
}
diff --git a/os/hal/ports/STM32L1xx/stm32_registry.h b/os/hal/ports/STM32L1xx/stm32_registry.h new file mode 100644 index 000000000..1a6379bcd --- /dev/null +++ b/os/hal/ports/STM32L1xx/stm32_registry.h @@ -0,0 +1,175 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/stm32_registry.h
+ * @brief STM32L1xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32L1xx capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 0
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1 TRUE
+#define STM32_HAS_DAC2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 23
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS FALSE
+#define STM32_RTC_IS_CALENDAR TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
|