diff options
Diffstat (limited to 'os/hal/ports')
-rw-r--r-- | os/hal/ports/STM32/LLD/DACv1/dac_lld.c | 16 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 225 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.h | 860 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32L4xx/platform.mk | 88 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32L4xx/stm32_registry.h | 301 |
5 files changed, 1482 insertions, 8 deletions
diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c index 6015c176c..faebcadc0 100644 --- a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c @@ -35,20 +35,20 @@ #define DAC1 DAC
#endif
-#define DAC1_CH1_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH1_DMA_STREAM, \
+#define DAC1_CH1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH1_DMA_STREAM, \
STM32_DAC1_CH1_DMA_CHN)
-#define DAC1_CH2_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH2_DMA_STREAM, \
+#define DAC1_CH2_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH2_DMA_STREAM, \
STM32_DAC1_CH2_DMA_CHN)
-#define DAC2_CH1_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH1_DMA_STREAM, \
+#define DAC2_CH1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH1_DMA_STREAM, \
STM32_DAC2_CH1_DMA_CHN)
-#define DAC2_CH2_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \
+#define DAC2_CH2_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \
STM32_DAC2_CH2_DMA_CHN)
#define CHANNEL_DATA_OFFSET 3U
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c new file mode 100644 index 000000000..0be1fa067 --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -0,0 +1,225 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/hal_lld.c
+ * @brief STM32L1xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+/* TODO: LSEBYP like in F3.*/
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32l1xx.h.
+ */
+uint32_t SystemCoreClock = STM32_SYSCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR |= PWR_CR_DBP;
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+ /* Backup domain reset.*/
+ RCC->CSR |= RCC_CSR_RTCRST;
+ RCC->CSR &= ~RCC_CSR_RTCRST;
+ }
+
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ RCC->CSR |= RCC_CSR_LSEON;
+ while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->CSR & RCC_CSR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->CSR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->CSR |= RCC_CSR_RTCEN;
+ }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Reset of all peripherals.*/
+ rccResetAHB(~RCC_AHBRSTR_FLITFRST);
+ rccResetAPB1(~RCC_APB1RSTR_PWRRST);
+ rccResetAPB2(~0);
+
+ /* PWR clock enabled.*/
+ rccEnablePWRInterface(FALSE);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+ /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+ PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief STM32L1xx voltage, clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+/**
+ * @brief Clocks and internal voltage initialization.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+ /* PWR clock enable.*/
+ RCC->APB1ENR = RCC_APB1ENR_PWREN;
+
+ /* Core voltage setup.*/
+ while ((PWR->CSR & PWR_CSR_VOSF) != 0)
+ ; /* Waits until regulator is stable. */
+ PWR->CR = STM32_VOS;
+ while ((PWR->CSR & PWR_CSR_VOSF) != 0)
+ ; /* Waits until regulator is stable. */
+
+ /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
+ always enabled because it is the fallback clock when PLL the fails.
+ Trim fields are not altered from reset values.*/
+ RCC->CFGR = 0;
+ RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
+ RCC->CR = RCC_CR_MSION;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ; /* Waits until MSI is stable. */
+
+#if STM32_HSI_ENABLED
+ /* HSI activation.*/
+ RCC->CR |= RCC_CR_HSION;
+ while ((RCC->CR & RCC_CR_HSIRDY) == 0)
+ ; /* Waits until HSI is stable. */
+#endif
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEBYP;
+#endif
+ /* HSE activation.*/
+ RCC->CR |= RCC_CR_HSEON;
+ while ((RCC->CR & RCC_CR_HSERDY) == 0)
+ ; /* Waits until HSE is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Waits until LSI is stable. */
+#endif
+
+#if STM32_LSE_ENABLED
+ /* LSE activation, have to unlock the register.*/
+ if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
+ PWR->CR |= PWR_CR_DBP;
+ RCC->CSR |= RCC_CSR_LSEON;
+ PWR->CR &= ~PWR_CR_DBP;
+ }
+ while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ; /* Waits until PLL is stable. */
+#endif
+
+ /* Other clock-related settings (dividers, MCO etc).*/
+ RCC->CR |= STM32_RTCPRE;
+ RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
+ STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+ RCC->CSR |= STM32_RTCSEL;
+
+ /* Flash setup and final clock selection.*/
+#if defined(STM32_FLASHBITS1)
+ FLASH->ACR = STM32_FLASHBITS1;
+#endif
+#if defined(STM32_FLASHBITS2)
+ FLASH->ACR = STM32_FLASHBITS2;
+#endif
+
+ /* Switching to the configured clock source if it is different from MSI.*/
+#if (STM32_SW != STM32_SW_MSI)
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+#endif
+#endif /* STM32_NO_INIT */
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+}
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h new file mode 100644 index 000000000..fb3b4d72c --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -0,0 +1,860 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/hal_lld.h
+ * @brief STM32L1xx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32L100xB, STM32L100xBA, STM32L100xC.
+ * - STM32L151xB, STM32L151xBA, STM32L151xC, STM32L151xCA,
+ * STM32L151xD, STM32L151xDX, STM32L151xE.
+ * - STM32L152xB, STM32L152xBA, STM32L152xC, STM32L152xCA,
+ * STM32L152xD, STM32L152xDX, STM32L152xE.
+ * - STM32L162xC, STM32L162xCA, STM32L162xD, STM32L162xDX,
+ * STM32L162xE.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#if defined(STM32L100xB) || defined(STM32L151xB) || \
+ defined(STM32L152xB) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density"
+
+#elif defined(STM32L100xBA) || defined(STM32L100xC) || \
+ defined(STM32L151xBA) || defined(STM32L151xC) || \
+ defined(STM32L151xCA) || defined(STM32L152xBA) || \
+ defined(STM32L152xC) || defined(STM32L152xCA) || \
+ defined(STM32L162xC) || defined(STM32L162xCA)
+#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density Plus"
+
+#elif defined(STM32L151xD) || defined(STM32L151xDX) || \
+ defined(STM32L151xE) || defined(STM32L152xD) || \
+ defined(STM32L152xDX) || defined(STM32L152xE) || \
+ defined(STM32L162xD) || defined(STM32L162xDX) || \
+ defined(STM32L162xE)
+#define PLATFORM_NAME "STM32L1xx Ultra Low Power High Density"
+
+#else
+#error "STM32L1xx device not specified"
+#endif
+
+/**
+ * @brief Sub-family identifier.
+ */
+#if !defined(STM32L1XX) || defined(__DOXYGEN__)
+#define STM32L1XX
+#endif
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK 16000000 /**< High speed internal clock. */
+#define STM32_LSICLK 38000 /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */
+#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */
+#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
+#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */
+
+#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
+#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
+/** @} */
+
+/**
+ * @name RCC_CR register bits definitions
+ * @{
+ */
+#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */
+#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */
+#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */
+#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */
+#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
+#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */
+#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
+#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
+#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
+#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
+#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
+
+#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
+#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
+#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
+#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
+#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
+
+#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
+#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
+
+#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_HSI (2 << 24) /**< HSI clock on MCO pin. */
+#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */
+#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
+#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
+#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
+
+#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */
+/** @} */
+
+/**
+ * @name RCC_ICSCR register bits definitions
+ * @{
+ */
+#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
+#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */
+#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */
+#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */
+#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */
+#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
+#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
+#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
+/** @} */
+
+/**
+ * @name RCC_CSR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
+#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
+#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
+#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
+#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Core voltage selection.
+ * @note This setting affects all the performance and clock related
+ * settings, the maximum performance is only obtainable selecting
+ * the maximum voltage.
+ */
+#if !defined(STM32_VOS) || defined(__DOXYGEN__)
+#define STM32_VOS STM32_VOS_1P8
+#endif
+
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief ADC clock setting.
+ */
+#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_ADC_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_ENABLED TRUE
+#endif
+
+/**
+ * @brief MSI frequency setting.
+ */
+#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
+#define STM32_MSIRANGE STM32_MSIRANGE_2M
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_HSI
+#endif
+
+/**
+ * @brief PLL multiplier value.
+ * @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE 6
+#endif
+
+/**
+ * @brief PLL divider value.
+ * @note The allowed values are 2, 3, 4.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLDIV_VALUE 3
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 32MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#endif
+
+/**
+ * @brief MCO clock source.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief RTC/LCD clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSE
+#endif
+
+/**
+ * @brief HSE divider toward RTC setting.
+ */
+#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
+#define STM32_RTCPRE STM32_RTCPRE_DIV2
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32L1xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L1xx_MCUCONF not defined"
+#endif
+
+/* Voltage related limits.*/
+#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
+/**
+ * @brief Maximum HSE clock frequency at current voltage setting.
+ */
+#define STM32_HSECLK_MAX 32000000
+
+/**
+ * @brief Maximum SYSCLK clock frequency at current voltage setting.
+ */
+#define STM32_SYSCLK_MAX 32000000
+
+/**
+ * @brief Maximum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MAX 96000000
+
+/**
+ * @brief Minimum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MIN 6000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX 32000000
+
+/**
+ * @brief Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX 32000000
+
+/**
+ * @brief Maximum frequency not requiring a wait state for flash accesses.
+ */
+#define STM32_0WS_THRESHOLD 16000000
+
+/**
+ * @brief HSI availability at current voltage settings.
+ */
+#define STM32_HSI_AVAILABLE TRUE
+
+#elif STM32_VOS == STM32_VOS_1P5
+#define STM32_HSECLK_MAX 16000000
+#define STM32_SYSCLK_MAX 16000000
+#define STM32_PLLVCO_MAX 48000000
+#define STM32_PLLVCO_MIN 6000000
+#define STM32_PCLK1_MAX 16000000
+#define STM32_PCLK2_MAX 16000000
+#define STM32_0WS_THRESHOLD 8000000
+#define STM32_HSI_AVAILABLE TRUE
+#elif STM32_VOS == STM32_VOS_1P2
+#define STM32_HSECLK_MAX 4000000
+#define STM32_SYSCLK_MAX 4000000
+#define STM32_PLLVCO_MAX 24000000
+#define STM32_PLLVCO_MIN 6000000
+#define STM32_PCLK1_MAX 4000000
+#define STM32_PCLK2_MAX 4000000
+#define STM32_0WS_THRESHOLD 2000000
+#define STM32_HSI_AVAILABLE FALSE
+#else
+#error "invalid STM32_VOS value specified"
+#endif
+
+/* HSI related checks.*/
+#if STM32_HSI_ENABLED
+#if !STM32_HSI_AVAILABLE
+ #error "impossible to activate HSI under the current voltage settings"
+#endif
+#else /* !STM32_HSI_ENABLED */
+#if STM32_ADC_CLOCK_ENABLED || \
+ (STM32_SW == STM32_SW_HSI) || \
+ ((STM32_SW == STM32_SW_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)) || \
+ (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "required HSI clock is not enabled"
+#endif
+#endif /* !STM32_HSI_ENABLED */
+
+/* HSE related checks.*/
+#if STM32_HSE_ENABLED
+#if STM32_HSECLK == 0
+#error "impossible to activate HSE"
+#endif
+#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
+#endif
+#else /* !STM32_HSE_ENABLED */
+#if (STM32_SW == STM32_SW_HSE) || \
+ ((STM32_SW == STM32_SW_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
+ (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
+ (STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
+#error "required HSE clock is not enabled"
+#endif
+#endif /* !STM32_HSE_ENABLED */
+
+/* LSI related checks.*/
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_LSI
+#error "LSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/* LSE related checks.*/
+#if STM32_LSE_ENABLED
+#if (STM32_LSECLK == 0)
+#error "impossible to activate LSE"
+#endif
+#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
+#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
+#endif
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_LSE
+#error "LSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL related checks.*/
+#if STM32_USB_CLOCK_ENABLED || \
+ (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/**
+ * @brief PLLMUL field.
+ */
+#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)
+#define STM32_PLLMUL (0 << 18)
+#elif STM32_PLLMUL_VALUE == 4
+#define STM32_PLLMUL (1 << 18)
+#elif STM32_PLLMUL_VALUE == 6
+#define STM32_PLLMUL (2 << 18)
+#elif STM32_PLLMUL_VALUE == 8
+#define STM32_PLLMUL (3 << 18)
+#elif STM32_PLLMUL_VALUE == 12
+#define STM32_PLLMUL (4 << 18)
+#elif STM32_PLLMUL_VALUE == 16
+#define STM32_PLLMUL (5 << 18)
+#elif STM32_PLLMUL_VALUE == 24
+#define STM32_PLLMUL (6 << 18)
+#elif STM32_PLLMUL_VALUE == 32
+#define STM32_PLLMUL (7 << 18)
+#elif STM32_PLLMUL_VALUE == 48
+#define STM32_PLLMUL (8 << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLDIV field.
+ */
+#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLDIV (1 << 22)
+#elif STM32_PLLDIV_VALUE == 3
+#define STM32_PLLDIV (2 << 22)
+#elif STM32_PLLDIV_VALUE == 4
+#define STM32_PLLDIV (3 << 22)
+#else
+#error "invalid STM32_PLLDIV_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN STM32_HSECLK
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN STM32_HSICLK
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000)
+#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)"
+#endif
+
+/**
+ * @brief PLL VCO frequency.
+ */
+#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000)
+#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"
+#endif
+
+/**
+ * @brief MSI frequency.
+ * @note Values are taken from the STM8Lxx datasheet.
+ */
+#if STM32_MSIRANGE == STM32_MSIRANGE_64K
+#define STM32_MSICLK 65500
+#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
+#define STM32_MSICLK 131000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
+#define STM32_MSICLK 262000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
+#define STM32_MSICLK 524000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
+#define STM32_MSICLK 1050000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
+#define STM32_MSICLK 2100000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
+#define STM32_MSICLK 4200000
+#else
+#error "invalid STM32_MSIRANGE value specified"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+#define STM32_SYSCLK 2100000
+#elif (STM32_SW == STM32_SW_MSI)
+#define STM32_SYSCLK STM32_MSICLK
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+#elif (STM32_SW == STM32_SW_PLL)
+#define STM32_SYSCLK STM32_PLLCLKOUT
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief MCO divider clock.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_MCODIVCLK 0
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI
+#define STM32_MCODIVCLK STM32_HSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_MSI
+#define STM32_MCODIVCLK STM32_MSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+#define STM32_MCODIVCLK STM32_HSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_PLL
+#define STM32_MCODIVCLK STM32_PLLCLKOUT
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+#define STM32_MCODIVCLK STM32_LSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+#define STM32_MCODIVCLK STM32_LSECLK
+#else
+#error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief MCO output pin clock.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCOCLK STM32_MCODIVCLK
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
+#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
+#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
+#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
+#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
+/**
+ * @brief HSE divider toward RTC clock.
+ */
+#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 2)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 4)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 8)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 16)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief RTC/LCD clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK 0
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK STM32_HSEDIVCLK
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief USB frequency.
+ */
+#define STM32_USBCLK (STM32_PLLVCO / 2)
+
+/**
+ * @brief Timers 2, 3, 4, 6, 7 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Timers 9, 10, 11 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS1 0x00000000
+#else
+#define STM32_FLASHBITS1 0x00000004
+#define STM32_FLASHBITS2 0x00000007
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk new file mode 100644 index 000000000..20422b67b --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -0,0 +1,88 @@ +# List of all the STM32L4xx platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+HALCONF := $(strip $(shell cat halconf.h | egrep -e "define"))
+
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c
+endif
+ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c
+endif
+ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
+endif
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c
+endif
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c
+endif
+ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c
+endif
+ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c
+endif
+ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c
+endif
+ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
+endif
+ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c
+endif
+ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c
+endif
+ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c
+endif
+ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c
+endif
+ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+endif
+else
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+endif
+
+# Required include directories
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h new file mode 100644 index 000000000..747ee52e6 --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -0,0 +1,301 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/stm32_registry.h
+ * @brief STM32L0xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32L4xx capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00005600
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_DAC1_CH1_DMA_CHN 0x00033000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 7
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH6_HANDLER Vector150
+#define STM32_DMA2_CH7_HANDLER Vector154
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+#define STM32_DMA2_CH6_NUMBER 68
+#define STM32_DMA2_CH7_NUMBER 69
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 39
+#define STM32_EXTI_IMR_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
+
+#define STM32_EXTI_LINE0_HANDLER Vector58
+#define STM32_EXTI_LINE1_HANDLER Vector5C
+#define STM32_EXTI_LINE2_HANDLER Vector60
+#define STM32_EXTI_LINE3_HANDLER Vector64
+#define STM32_EXTI_LINE4_HANDLER Vector68
+#define STM32_EXTI_LINE5_9_HANDLER Vector9C
+#define STM32_EXTI_LINE10_15_HANDLER VectorE0
+
+#define STM32_EXTI_LINE0_NUMBER 6
+#define STM32_EXTI_LINE1_NUMBER 7
+#define STM32_EXTI_LINE2_NUMBER 8
+#define STM32_EXTI_LINE3_NUMBER 9
+#define STM32_EXTI_LINE4_NUMBER 10
+#define STM32_EXTI_LINE5_9_NUMBER 23
+#define STM32_EXTI_LINE10_15_NUMBER 40
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
+ RCC_IOPENR_GPIOBEN | \
+ RCC_IOPENR_GPIOCEN | \
+ RCC_IOPENR_GPIODEN | \
+ RCC_IOPENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
+#define STM32_RTC_NUM_ALARMS 1
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS FALSE
+#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
+
+#define STM32_HAS_TIM21 TRUE
+#define STM32_TIM21_IS_32BITS FALSE
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
+
+#define STM32_HAS_TIM1 FALSE
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x04004000
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
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