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-rw-r--r--os/hal/ports/STM32/STM32F0xx/stm32_registry.h54
-rw-r--r--os/hal/ports/STM32/STM32F1xx/stm32_registry.h63
-rw-r--r--os/hal/ports/STM32/STM32F37x/stm32_registry.h18
-rw-r--r--os/hal/ports/STM32/STM32F3xx/stm32_registry.h81
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld.c11
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld.h53
-rw-r--r--os/hal/ports/STM32/STM32F4xx/stm32_isr.h16
-rw-r--r--os/hal/ports/STM32/STM32F4xx/stm32_rcc.h30
-rw-r--r--os/hal/ports/STM32/STM32F4xx/stm32_registry.h28
-rw-r--r--os/hal/ports/STM32/STM32L1xx/stm32_registry.h18
10 files changed, 372 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
index a36ec839b..bb18a6e81 100644
--- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
@@ -190,6 +190,15 @@
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
/*===========================================================================*/
/* STM32F071xB, STM32F072xB, STM32F078xx. */
/*===========================================================================*/
@@ -362,6 +371,15 @@
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
/*===========================================================================*/
/* STM32F048xx. */
/*===========================================================================*/
@@ -505,6 +523,15 @@
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
/*===========================================================================*/
/* STM32F031x6, STM32F038xx. */
/*===========================================================================*/
@@ -646,6 +673,15 @@
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
/*===========================================================================*/
/* STM32F042x6. */
/*===========================================================================*/
@@ -785,6 +821,15 @@
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
/*===========================================================================*/
/* STM32F030x6, STM32F030x8. */
/*===========================================================================*/
@@ -935,6 +980,15 @@
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
#else
#error "STM32F0xx device not specified"
#endif
diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
index 85a693bf7..8eeab9747 100644
--- a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
@@ -173,6 +173,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
/** @} */
#endif /* defined(STM32F10X_LD_VL) */
@@ -332,6 +341,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
/** @} */
#endif /* defined(STM32F10X_MD_VL) */
@@ -460,6 +478,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
/** @} */
#endif /* defined(STM32F10X_LD) */
@@ -603,6 +630,15 @@
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
/** @} */
#endif /* defined(STM32F10X_MD) */
@@ -786,6 +822,15 @@
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
/** @} */
#endif /* defined(STM32F10X_HD) */
@@ -969,6 +1014,15 @@
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
/** @} */
#endif /* defined(STM32F10X_XL) */
@@ -1129,6 +1183,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
/** @} */
#endif /* defined(STM32F10X_CL) */
diff --git a/os/hal/ports/STM32/STM32F37x/stm32_registry.h b/os/hal/ports/STM32/STM32F37x/stm32_registry.h
index 68db85acb..86e6b0d37 100644
--- a/os/hal/ports/STM32/STM32F37x/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F37x/stm32_registry.h
@@ -219,6 +219,15 @@
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F373xC) */
/*===========================================================================*/
@@ -406,6 +415,15 @@
#define STM32_USB_PMA_SIZE 512
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F378xx) */
/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
index d3a130995..3176cd567 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
@@ -216,6 +216,15 @@
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F303xC) */
/*===========================================================================*/
@@ -376,6 +385,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F303x8) */
/*===========================================================================*/
@@ -531,6 +549,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F301x8) */
/*===========================================================================*/
@@ -689,6 +716,15 @@
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F302x8) */
/*===========================================================================*/
@@ -859,6 +895,15 @@
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F302xC) */
/*===========================================================================*/
@@ -1013,6 +1058,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F318x8) */
/*===========================================================================*/
@@ -1170,6 +1224,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F328x8) */
/*===========================================================================*/
@@ -1342,6 +1405,15 @@
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F358xC) */
/*===========================================================================*/
@@ -1499,6 +1571,15 @@
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
#endif /* defined(STM32F334x8) */
/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 4bb3f4fcd..03cd5f06f 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -232,6 +232,17 @@ void stm32_clock_init(void) {
;
#endif
+#if STM32_ACTIVATE_PLLSAI
+ /* PLLSAI activation.*/
+ RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ;
+ RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
+ RCC->CR |= RCC_CR_PLLSAION;
+
+ /* Waiting for PLL lock.*/
+ while (!(RCC->CR & RCC_CR_PLLSAIRDY))
+ ;
+#endif
+
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index c466a8274..ab5a327de 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -362,6 +362,13 @@
#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
+#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
+#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
+#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
+#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
+#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
+#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
+
#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
@@ -1278,6 +1285,52 @@
#error "invalid STM32_PLLI2SR_VALUE value specified"
#endif
+/*
+ * PLLSAI enable check.
+ */
+#if !defined(STM32_SAISRC)
+#define STM32_SAISRC STM32_SAISRC_NOCLOCK
+#endif
+
+/**
+ * @brief PLL activation flag.
+ */
+#if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__)
+#define STM32_ACTIVATE_PLLSAI TRUE
+#else
+#define STM32_ACTIVATE_PLLSAI FALSE
+#endif
+
+/**
+ * @brief STM32_PLLSAIN field.
+ */
+#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6)
+#else
+#error "invalid STM32_PLLSAIN_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIQ field.
+ */
+#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24)
+#else
+#error "invalid STM32_PLLSAIR_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAIR field.
+ */
+#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28)
+#else
+#error "invalid STM32_PLLSAIR_VALUE value specified"
+#endif
+
/**
* @brief PLL VCO frequency.
*/
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
index 1c9a90a0a..548fc62c7 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
@@ -158,6 +158,22 @@
#define STM32_FSMC_NUMBER 48
+/*
+ * LTDC
+ */
+#define STM32_LTDC_EV_HANDLER Vector1A0
+#define STM32_LTDC_ER_HANDLER Vector1A4
+
+#define STM32_LTDC_EV_NUMBER 88
+#define STM32_LTDC_ER_NUMBER 89
+
+/*
+ * DMA2D
+ */
+#define STM32_DMA2D_HANDLER Vector1A8
+
+#define STM32_DMA2D_NUMBER 90
+
/** @} */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
index 393fa5994..b86c85d58 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
@@ -1468,6 +1468,36 @@
#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)
/**
+ * @name DMA2D peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA2D peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
+
+/**
+ * @brief Disables the DMA2D peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
+
+/**
+ * @brief Resets the DMA2D peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)
+/** @} */
+
+/**
* @name FSMC peripherals specific RCC operations
* @{
*/
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
index b875fe02a..c3fa55879 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -322,6 +322,12 @@
#define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 TRUE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC TRUE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+
/* FSMC attributes.*/
#define STM32_HAS_FSMC TRUE
#define STM32_FSMC_IS_FMC TRUE
@@ -334,6 +340,7 @@
STM32_DMA_STREAM_ID_MSK(2, 6) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_FSMC_DMA_CHN 0x03010201
+
#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
/*===========================================================================*/
@@ -591,6 +598,12 @@
#define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 TRUE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
/* FSMC attributes.*/
#define STM32_HAS_FSMC TRUE
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
@@ -602,6 +615,7 @@
STM32_DMA_STREAM_ID_MSK(2, 6) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_FSMC_DMA_CHN 0x03010201
+
#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */
/*===========================================================================*/
@@ -815,8 +829,15 @@
#define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
/* FSMC attributes.*/
#define STM32_HAS_FSMC FALSE
+
#endif /* defined(STM32F401xx) */
/*===========================================================================*/
@@ -1029,8 +1050,15 @@
#define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
/* FSMC attributes.*/
#define STM32_HAS_FSMC FALSE
+
#endif
/** @} */
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
index 4c5067db5..129f4c871 100644
--- a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
@@ -190,6 +190,15 @@
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
#else /* STM32L1XX_HD */
/* ADC attributes.*/
@@ -355,6 +364,15 @@
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
#endif /* STM32L1XX_HD */
/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-15 13:39:10 +0000