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-rw-r--r--os/hal/ports/STM32/STM32L4xx+/hal_lld.h5
-rw-r--r--os/hal/ports/STM32/STM32L4xx+/platform.mk1
-rw-r--r--os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h28
-rw-r--r--os/hal/ports/STM32/STM32L4xx+/stm32_registry.h3
4 files changed, 37 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
index df8515aa8..23723d822 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
@@ -2138,6 +2138,11 @@
#define STM32_USBCLK STM32_48CLK
/**
+ * @brief RNG clock point.
+ */
+#define STM32_RNGCLK STM32_48CLK
+
+/**
* @brief ADC clock frequency.
*/
#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__)
diff --git a/os/hal/ports/STM32/STM32L4xx+/platform.mk b/os/hal/ports/STM32/STM32L4xx+/platform.mk
index d4b905ea0..aaf6b7910 100644
--- a/os/hal/ports/STM32/STM32L4xx+/platform.mk
+++ b/os/hal/ports/STM32/STM32L4xx+/platform.mk
@@ -27,6 +27,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h
index b72ee0f29..56c261c76 100644
--- a/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h
@@ -626,6 +626,34 @@
/** @} */
/**
+ * @name RNG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the RNG peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
+
+/**
+ * @brief Disables the RNG peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
+
+/**
+ * @brief Resets the RNG peripheral.
+ *
+ * @api
+ */
+#define rccResetRNG() rccResetAHB3(RCC_AHB2RSTR_RNGRST)
+/** @} */
+
+/**
* @name SDMMC peripheral specific RCC operations
* @{
*/
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
index f31872e86..c6b4432a9 100644
--- a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
@@ -194,6 +194,9 @@
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
+/* RNG attributes.*/
+#define STM32_HAS_RNG1 TRUE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE