diff options
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx/stm32_registry.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_registry.h | 146 |
1 files changed, 141 insertions, 5 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h index 7025ad7bb..2ed95fc0e 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h @@ -61,13 +61,37 @@ #define STM32_HAS_SDADC3 FALSE
/* CAN attributes.*/
+#define STM32_CAN_MAX_FILTERS 28
+
#define STM32_HAS_CAN1 TRUE
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+
#define STM32_HAS_CAN2 TRUE
-#define STM32_CAN_MAX_FILTERS 28
+#define STM32_CAN2_TX_HANDLER Vector13C
+#define STM32_CAN2_RX0_HANDLER Vector140
+#define STM32_CAN2_RX1_HANDLER Vector144
+#define STM32_CAN2_SCE_HANDLER Vector148
+#define STM32_CAN2_TX_NUMBER 63
+#define STM32_CAN2_RX0_NUMBER 64
+#define STM32_CAN2_RX1_NUMBER 65
+#define STM32_CAN2_SCE_NUMBER 66
/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_DAC1_CH1_DMA_CHN 0x00070000
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_DAC1_CH2_DMA_CHN 0x00700000
+
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
@@ -78,6 +102,8 @@ /* ETH attributes.*/
#define STM32_HAS_ETH TRUE
+#define STM32_ETH_HANDLER Vector134
+#define STM32_ETH_NUMBER 61
/* EXTI attributes.*/
#define STM32_EXTI_NUM_CHANNELS 23
@@ -92,6 +118,8 @@ #define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOI TRUE
+#define STM32_HAS_GPIOJ TRUE
+#define STM32_HAS_GPIOK TRUE
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | \
@@ -100,10 +128,16 @@ RCC_AHB1ENR_GPIOFEN | \
RCC_AHB1ENR_GPIOGEN | \
RCC_AHB1ENR_GPIOHEN | \
- RCC_AHB1ENR_GPIOIEN)
+ RCC_AHB1ENR_GPIOIEN | \
+ RCC_AHB1ENR_GPIOJEN | \
+ RCC_AHB1ENR_GPIOKEN)
/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_NUMBER 32
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_I2C1_RX_DMA_CHN 0x00100001
@@ -112,6 +146,10 @@ #define STM32_I2C1_TX_DMA_CHN 0x11000000
#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_NUMBER 34
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_I2C2_RX_DMA_CHN 0x00007700
@@ -119,11 +157,25 @@ #define STM32_I2C2_TX_DMA_CHN 0x70000000
#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_NUMBER 73
#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_I2C3_RX_DMA_CHN 0x00000300
#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_I2C3_TX_DMA_CHN 0x00030000
+#define STM32_HAS_I2C4 TRUE
+#define STM32_I2C4_EVENT_HANDLER Vector1BC
+#define STM32_I2C4_ERROR_HANDLER Vector1C0
+#define STM32_I2C4_EVENT_NUMBER 95
+#define STM32_I2C4_ERROR_NUMBER 96
+#define STM32_I2C4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C4_RX_DMA_CHN 0x00000200
+#define STM32_I2C4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C4_TX_DMA_CHN 0x00200000
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -133,6 +185,8 @@ /* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
+#define STM32_SDIO_HANDLER Vector104
+#define STM32_SDIO_NUMBER 49
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 6))
#define STM32_SDC_SDIO_DMA_CHN 0x04004000
@@ -188,58 +242,90 @@ #define STM32_HAS_TIM1 TRUE
#define STM32_TIM1_IS_32BITS FALSE
#define STM32_TIM1_CHANNELS 4
+#define STM32_TIM1_UP_HANDLER VectorA4
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM1_UP_NUMBER 25
+#define STM32_TIM1_CC_NUMBER 27
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS TRUE
#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM2_NUMBER 28
#define STM32_HAS_TIM3 TRUE
#define STM32_TIM3_IS_32BITS FALSE
#define STM32_TIM3_CHANNELS 4
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM3_NUMBER 29
#define STM32_HAS_TIM4 TRUE
#define STM32_TIM4_IS_32BITS FALSE
#define STM32_TIM4_CHANNELS 4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM4_NUMBER 30
#define STM32_HAS_TIM5 TRUE
#define STM32_TIM5_IS_32BITS TRUE
#define STM32_TIM5_CHANNELS 4
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM5_NUMBER 50
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM6_NUMBER 54
#define STM32_HAS_TIM7 TRUE
#define STM32_TIM7_IS_32BITS FALSE
#define STM32_TIM7_CHANNELS 0
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM7_NUMBER 55
#define STM32_HAS_TIM8 TRUE
#define STM32_TIM8_IS_32BITS FALSE
#define STM32_TIM8_CHANNELS 6
+#define STM32_TIM8_UP_HANDLER VectorF0
+#define STM32_TIM8_CC_HANDLER VectorF8
+#define STM32_TIM8_UP_NUMBER 44
+#define STM32_TIM8_CC_NUMBER 46
#define STM32_HAS_TIM9 TRUE
#define STM32_TIM9_IS_32BITS FALSE
#define STM32_TIM9_CHANNELS 2
+#define STM32_TIM9_HANDLER VectorA0
+#define STM32_TIM9_NUMBER 24
#define STM32_HAS_TIM10 TRUE
#define STM32_TIM10_IS_32BITS FALSE
#define STM32_TIM10_CHANNELS 2
+#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */
+#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */
#define STM32_HAS_TIM11 TRUE
#define STM32_TIM11_IS_32BITS FALSE
#define STM32_TIM11_CHANNELS 2
+#define STM32_TIM11_HANDLER VectorA8
+#define STM32_TIM11_NUMBER 26
#define STM32_HAS_TIM12 TRUE
#define STM32_TIM12_IS_32BITS FALSE
#define STM32_TIM12_CHANNELS 2
+#define STM32_TIM12_HANDLER VectorEC
+#define STM32_TIM12_NUMBER 43
#define STM32_HAS_TIM13 TRUE
#define STM32_TIM13_IS_32BITS FALSE
#define STM32_TIM13_CHANNELS 2
+#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */
+#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */
#define STM32_HAS_TIM14 TRUE
#define STM32_TIM14_IS_32BITS FALSE
#define STM32_TIM14_CHANNELS 2
+#define STM32_TIM14_HANDLER VectorF4
+#define STM32_TIM14_NUMBER 45
#define STM32_HAS_TIM15 FALSE
#define STM32_HAS_TIM16 FALSE
@@ -252,6 +338,8 @@ /* USART attributes.*/
#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART1_NUMBER 37
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_USART1_RX_DMA_CHN 0x00400400
@@ -259,12 +347,16 @@ #define STM32_USART1_TX_DMA_CHN 0x40000000
#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART2_NUMBER 38
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
#define STM32_USART2_RX_DMA_CHN 0x00400000
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
#define STM32_USART2_TX_DMA_CHN 0x04000000
#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_USART3_NUMBER 39
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
#define STM32_USART3_RX_DMA_CHN 0x00000040
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
@@ -272,18 +364,24 @@ #define STM32_USART3_TX_DMA_CHN 0x00074000
#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_HANDLER Vector110
+#define STM32_UART4_NUMBER 52
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_UART4_RX_DMA_CHN 0x00000400
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_UART4_TX_DMA_CHN 0x00040000
#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_HANDLER Vector114
+#define STM32_UART5_NUMBER 53
#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
#define STM32_UART5_RX_DMA_CHN 0x00000004
#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
#define STM32_UART5_TX_DMA_CHN 0x40000000
#define STM32_HAS_USART6 TRUE
+#define STM32_USART6_HANDLER Vector15C
+#define STM32_USART6_NUMBER 71
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_USART6_RX_DMA_CHN 0x00000550
@@ -291,10 +389,36 @@ STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_USART6_TX_DMA_CHN 0x55000000
+#define STM32_HAS_UART7 TRUE
+#define STM32_UART7_HANDLER Vector188
+#define STM32_UART7_NUMBER 83
+#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_UART7_RX_DMA_CHN 0x00005000
+#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_UART7_TX_DMA_CHN 0x00000050
+
+#define STM32_HAS_UART8 TRUE
+#define STM32_UART8_HANDLER Vector18C
+#define STM32_UART8_NUMBER 83
+#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_UART8_RX_DMA_CHN 0x05000000
+#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART8_TX_DMA_CHN 0x00000005
+
/* USB attributes.*/
#define STM32_HAS_USB FALSE
+
#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_HANDLER Vector14C
+#define STM32_OTG1_NUMBER 67
+
#define STM32_HAS_OTG2 TRUE
+#define STM32_OTG2_HANDLER Vector174
+#define STM32_OTG2_EP1OUT_HANDLER Vector168
+#define STM32_OTG2_EP1IN_HANDLER Vector16C
+#define STM32_OTG2_NUMBER 77
+#define STM32_OTG2_EP1OUT_NUMBER 74
+#define STM32_OTG2_EP1IN_NUMBER 75
/* LTDC attributes.*/
#define STM32_HAS_LTDC TRUE
@@ -305,6 +429,8 @@ /* FSMC attributes.*/
#define STM32_HAS_FSMC TRUE
#define STM32_FSMC_IS_FMC TRUE
+#define STM32_FSMC_HANDLER Vector100
+#define STM32_FSMC_NUMBER 48
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 1) |\
STM32_DMA_STREAM_ID_MSK(2, 2) |\
@@ -313,7 +439,17 @@ STM32_DMA_STREAM_ID_MSK(2, 5) |\
STM32_DMA_STREAM_ID_MSK(2, 6) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_FSMC_DMA_CHN 0x03010201
+#define STM32_FSMC_DMA_CHN 0x00000000
+
+/* LTDC attributes.*/
+#define STM32_LTDC_EV_HANDLER Vector1A0
+#define STM32_LTDC_ER_HANDLER Vector1A4
+#define STM32_LTDC_EV_NUMBER 88
+#define STM32_LTDC_ER_NUMBER 89
+
+/* DMA2D attributes.*/
+#define STM32_DMA2D_HANDLER Vector1A8
+#define STM32_DMA2D_NUMBER 90
/* CRC attributes.*/
#define STM32_HAS_CRC TRUE
|