diff options
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx/stm32_rcc.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_rcc.h | 252 |
1 files changed, 69 insertions, 183 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index 27e52e3a4..f0c7dfb99 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -23,8 +23,8 @@ * @addtogroup STM32F7xx_RCC
* @{
*/
-#ifndef _STM32_RCC_
-#define _STM32_RCC_
+#ifndef STM32_RCC_H
+#define STM32_RCC_H
/*===========================================================================*/
/* Driver constants. */
@@ -68,14 +68,12 @@ * @brief Disables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
- * @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableAPB1(mask, lp) { \
+#define rccDisableAPB1(mask) { \
RCC->APB1ENR &= ~(mask); \
- if (lp) \
- RCC->APB1LPENR &= ~(mask); \
+ RCC->APB1LPENR &= ~(mask); \
}
/**
@@ -108,14 +106,12 @@ * @brief Disables the clock of one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
- * @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableAPB2(mask, lp) { \
+#define rccDisableAPB2(mask) { \
RCC->APB2ENR &= ~(mask); \
- if (lp) \
- RCC->APB2LPENR &= ~(mask); \
+ RCC->APB2LPENR &= ~(mask); \
}
/**
@@ -148,14 +144,12 @@ * @brief Disables the clock of one or more peripheral on the AHB1 bus.
*
* @param[in] mask AHB1 peripherals mask
- * @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableAHB1(mask, lp) { \
+#define rccDisableAHB1(mask) { \
RCC->AHB1ENR &= ~(mask); \
- if (lp) \
- RCC->AHB1LPENR &= ~(mask); \
+ RCC->AHB1LPENR &= ~(mask); \
}
/**
@@ -188,14 +182,12 @@ * @brief Disables the clock of one or more peripheral on the AHB2 bus.
*
* @param[in] mask AHB2 peripherals mask
- * @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableAHB2(mask, lp) { \
+#define rccDisableAHB2(mask) { \
RCC->AHB2ENR &= ~(mask); \
- if (lp) \
- RCC->AHB2LPENR &= ~(mask); \
+ RCC->AHB2LPENR &= ~(mask); \
}
/**
@@ -228,14 +220,12 @@ * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
*
* @param[in] mask AHB3 peripherals mask
- * @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableAHB3(mask, lp) { \
+#define rccDisableAHB3(mask) { \
RCC->AHB3ENR &= ~(mask); \
- if (lp) \
- RCC->AHB3LPENR &= ~(mask); \
+ RCC->AHB3LPENR &= ~(mask); \
}
/**
@@ -267,11 +257,9 @@ /**
* @brief Disables the ADC1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
+#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
/**
* @brief Resets the ADC1 peripheral.
@@ -292,11 +280,9 @@ /**
* @brief Disables the ADC2 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp)
+#define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN)
/**
* @brief Resets the ADC2 peripheral.
@@ -317,11 +303,9 @@ /**
* @brief Disables the ADC3 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp)
+#define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN)
/**
* @brief Resets the ADC3 peripheral.
@@ -347,11 +331,9 @@ /**
* @brief Disables the DAC1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
+#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DACEN)
/**
* @brief Resets the DAC1 peripheral.
@@ -377,11 +359,9 @@ /**
* @brief Disables the DMA1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp)
+#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
/**
* @brief Resets the DMA1 peripheral.
@@ -402,11 +382,9 @@ /**
* @brief Disables the DMA2 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp)
+#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
/**
* @brief Resets the DMA2 peripheral.
@@ -432,11 +410,9 @@ /**
* @brief Disables the BKPSRAM peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableBKPSRAM(lp) rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)
+#define rccDisableBKPSRAM() rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN)
/** @} */
/**
@@ -455,11 +431,9 @@ /**
* @brief Disables PWR interface clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
/**
* @brief Resets the PWR interface.
@@ -485,11 +459,9 @@ /**
* @brief Disables the CAN1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
+#define rccDisableCAN1() rccDisableAPB1(RCC_APB1ENR_CAN1EN)
/**
* @brief Resets the CAN1 peripheral.
@@ -510,11 +482,9 @@ /**
* @brief Disables the CAN2 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)
+#define rccDisableCAN2() rccDisableAPB1(RCC_APB1ENR_CAN2EN)
/**
* @brief Resets the CAN2 peripheral.
@@ -542,11 +512,9 @@ /**
* @brief Disables the CAN3 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableCAN3(lp) rccDisableAPB1(RCC_APB1ENR_CAN3EN, lp)
+#define rccDisableCAN3() rccDisableAPB1(RCC_APB1ENR_CAN3EN)
/** @} */
/**
@@ -556,13 +524,11 @@ /**
* @brief Enables the ETH peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
RCC_AHB1ENR_ETHMACTXEN | \
- RCC_AHB1ENR_ETHMACRXEN, lp)
+ RCC_AHB1ENR_ETHMACRXEN)
/**
* @brief Disables the ETH peripheral clock.
@@ -571,9 +537,9 @@ *
* @api
*/
-#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
- RCC_AHB1ENR_ETHMACTXEN | \
- RCC_AHB1ENR_ETHMACRXEN, lp)
+#define rccDisableETH() rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
+ RCC_AHB1ENR_ETHMACTXEN | \
+ RCC_AHB1ENR_ETHMACRXEN)
/**
* @brief Resets the ETH peripheral.
@@ -599,11 +565,9 @@ /**
* @brief Disables the I2C1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
/**
* @brief Resets the I2C1 peripheral.
@@ -624,11 +588,9 @@ /**
* @brief Disables the I2C2 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
/**
* @brief Resets the I2C2 peripheral.
@@ -649,11 +611,9 @@ /**
* @brief Disables the I2C3 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp)
+#define rccDisableI2C3() rccDisableAPB1(RCC_APB1ENR_I2C3EN)
/**
* @brief Resets the I2C3 peripheral.
@@ -674,11 +634,9 @@ /**
* @brief Disables the I2C4 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableI2C4(lp) rccDisableAPB1(RCC_APB1ENR_I2C4EN, lp)
+#define rccDisableI2C4() rccDisableAPB1(RCC_APB1ENR_I2C4EN)
/**
* @brief Resets the I2C4 peripheral.
@@ -704,11 +662,9 @@ /**
* @brief Disables the OTG_FS peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
+#define rccDisableOTG_FS() rccDisableAHB2(RCC_AHB2ENR_OTGFSEN)
/**
* @brief Resets the OTG_FS peripheral.
@@ -729,11 +685,9 @@ /**
* @brief Disables the OTG_HS peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
+#define rccDisableOTG_HS() rccDisableAHB1(RCC_AHB1ENR_OTGHSEN)
/**
* @brief Resets the OTG_HS peripheral.
@@ -754,11 +708,9 @@ /**
* @brief Disables the OTG_HS peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
+#define rccDisableOTG_HSULPI() rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN)
/** @} */
/**
@@ -777,11 +729,9 @@ /**
* @brief Disables the QUADSPI1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
/**
* @brief Resets the QUADSPI1 peripheral.
@@ -807,11 +757,9 @@ /**
* @brief Disables the SDMMC1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableSDMMC1(lp) rccDisableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
+#define rccDisableSDMMC1() rccDisableAPB2(RCC_APB2ENR_SDMMC1EN)
/**
* @brief Resets the SDMMC1 peripheral.
@@ -837,11 +785,9 @@ /**
* @brief Disables the SPI1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
/**
* @brief Resets the SPI1 peripheral.
@@ -862,11 +808,9 @@ /**
* @brief Disables the SPI2 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
/**
* @brief Resets the SPI2 peripheral.
@@ -887,11 +831,9 @@ /**
* @brief Disables the SPI3 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+#define rccDisableSPI3() rccDisableAPB1(RCC_APB1ENR_SPI3EN)
/**
* @brief Resets the SPI3 peripheral.
@@ -912,11 +854,9 @@ /**
* @brief Disables the SPI4 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableSPI4(lp) rccDisableAPB2(RCC_APB2ENR_SPI4EN, lp)
+#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
/**
* @brief Resets the SPI4 peripheral.
@@ -937,11 +877,9 @@ /**
* @brief Disables the SPI5 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableSPI5(lp) rccDisableAPB2(RCC_APB2ENR_SPI5EN, lp)
+#define rccDisableSPI5() rccDisableAPB2(RCC_APB2ENR_SPI5EN)
/**
* @brief Resets the SPI5 peripheral.
@@ -962,11 +900,9 @@ /**
* @brief Disables the SPI6 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableSPI6(lp) rccDisableAPB2(RCC_APB2ENR_SPI6EN, lp)
+#define rccDisableSPI6() rccDisableAPB2(RCC_APB2ENR_SPI6EN)
/**
* @brief Resets the SPI6 peripheral.
@@ -992,11 +928,9 @@ /**
* @brief Disables the TIM1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
/**
* @brief Resets the TIM1 peripheral.
@@ -1017,11 +951,9 @@ /**
* @brief Disables the TIM2 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
/**
* @brief Resets the TIM2 peripheral.
@@ -1042,11 +974,9 @@ /**
* @brief Disables the TIM3 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
/**
* @brief Resets the TIM3 peripheral.
@@ -1067,11 +997,9 @@ /**
* @brief Disables the TIM4 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
/**
* @brief Resets the TIM4 peripheral.
@@ -1092,11 +1020,9 @@ /**
* @brief Disables the TIM5 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)
+#define rccDisableTIM5() rccDisableAPB1(RCC_APB1ENR_TIM5EN)
/**
* @brief Resets the TIM5 peripheral.
@@ -1117,11 +1043,9 @@ /**
* @brief Disables the TIM6 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
/**
* @brief Resets the TIM6 peripheral.
@@ -1142,11 +1066,9 @@ /**
* @brief Disables the TIM7 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
/**
* @brief Resets the TIM7 peripheral.
@@ -1167,11 +1089,9 @@ /**
* @brief Disables the TIM8 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
/**
* @brief Resets the TIM8 peripheral.
@@ -1192,11 +1112,9 @@ /**
* @brief Disables the TIM9 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)
+#define rccDisableTIM9() rccDisableAPB2(RCC_APB2ENR_TIM9EN)
/**
* @brief Resets the TIM9 peripheral.
@@ -1217,11 +1135,9 @@ /**
* @brief Disables the TIM10 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
+#define rccDisableTIM10() rccDisableAPB2(RCC_APB2ENR_TIM10EN)
/**
* @brief Resets the TIM10 peripheral.
@@ -1242,11 +1158,9 @@ /**
* @brief Disables the TIM11 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp)
+#define rccDisableTIM11() rccDisableAPB2(RCC_APB2ENR_TIM11EN)
/**
* @brief Resets the TIM11 peripheral.
@@ -1267,11 +1181,9 @@ /**
* @brief Disables the TIM12 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp)
+#define rccDisableTIM12() rccDisableAPB1(RCC_APB1ENR_TIM12EN)
/**
* @brief Resets the TIM12 peripheral.
@@ -1292,11 +1204,9 @@ /**
* @brief Disables the TIM13 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)
+#define rccDisableTIM13() rccDisableAPB1(RCC_APB1ENR_TIM13EN)
/**
* @brief Resets the TIM13 peripheral.
@@ -1317,11 +1227,9 @@ /**
* @brief Disables the TIM14 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp)
+#define rccDisableTIM14() rccDisableAPB1(RCC_APB1ENR_TIM14EN)
/**
* @brief Resets the TIM14 peripheral.
@@ -1347,11 +1255,9 @@ /**
* @brief Disables the USART1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
/**
* @brief Resets the USART1 peripheral.
@@ -1372,11 +1278,9 @@ /**
* @brief Disables the USART2 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
/**
* @brief Resets the USART2 peripheral.
@@ -1397,11 +1301,9 @@ /**
* @brief Disables the USART3 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
/**
* @brief Resets the USART3 peripheral.
@@ -1422,11 +1324,9 @@ /**
* @brief Disables the UART4 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
+#define rccDisableUART4() rccDisableAPB1(RCC_APB1ENR_UART4EN)
/**
* @brief Resets the UART4 peripheral.
@@ -1447,11 +1347,9 @@ /**
* @brief Disables the UART5 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
+#define rccDisableUART5() rccDisableAPB1(RCC_APB1ENR_UART5EN)
/**
* @brief Resets the UART5 peripheral.
@@ -1472,11 +1370,9 @@ /**
* @brief Disables the USART6 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)
+#define rccDisableUSART6() rccDisableAPB2(RCC_APB2ENR_USART6EN)
/**
* @brief Resets the USART6 peripheral.
@@ -1497,11 +1393,9 @@ /**
* @brief Disables the UART7 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableUART7(lp) rccDisableAPB1(RCC_APB1ENR_UART7EN, lp)
+#define rccDisableUART7() rccDisableAPB1(RCC_APB1ENR_UART7EN)
/**
* @brief Resets the UART7 peripheral.
@@ -1522,11 +1416,9 @@ /**
* @brief Disables the UART8 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableUART8(lp) rccDisableAPB1(RCC_APB1ENR_UART8EN, lp)
+#define rccDisableUART8() rccDisableAPB1(RCC_APB1ENR_UART8EN)
/**
* @brief Resets the UART8 peripheral.
@@ -1552,11 +1444,9 @@ /**
* @brief Disables the LTDC peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableLTDC(lp) rccDisableAPB2(RCC_APB2ENR_LTDCEN, lp)
+#define rccDisableLTDC() rccDisableAPB2(RCC_APB2ENR_LTDCEN)
/**
* @brief Resets the LTDC peripheral.
@@ -1581,11 +1471,9 @@ /**
* @brief Disables the DMA2D peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
+#define rccDisableDMA2D() rccDisableAHB1(RCC_AHB1ENR_DMA2DEN)
/**
* @brief Resets the DMA2D peripheral.
@@ -1615,14 +1503,12 @@ /**
* @brief Disables the FSMC peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
#if defined(STM32_FSMC_IS_FMC)
- #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp)
+ #define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FMCEN)
#else
- #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FSMCEN, lp)
+ #define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FSMCEN)
#endif
/**
@@ -1648,6 +1534,6 @@ extern "C" { }
#endif
-#endif /* _STM32_RCC_ */
+#endif /* STM32_RCC_H */
/** @} */
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