1 files changed, 43 insertions, 6 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index aa38fb39e..91583f263 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -176,7 +176,7 @@ void stm32_clock_init(void) {
   /* Registers finally cleared to reset values.*/
   RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
   RCC->CFGR = 0;                            /* CFGR reset value.            */
-
+  
 #if STM32_HSE_ENABLED
   /* HSE activation.*/
 #if defined(STM32_HSE_BYPASS)
@@ -223,7 +223,7 @@ void stm32_clock_init(void) {
   /* Waiting for PLL lock.*/
   while (!(RCC->CR & RCC_CR_PLLRDY))
     ;
-#endif /* STM32_OVERDRIVE_REQUIRED */
+#endif /* STM32_ACTIVATE_PLL */
 
 #if STM32_ACTIVATE_PLLI2S
   /* PLLI2S activation.*/
@@ -234,24 +234,61 @@ void stm32_clock_init(void) {
   /* Waiting for PLL lock.*/
   while (!(RCC->CR & RCC_CR_PLLI2SRDY))
     ;
-#endif
+#endif /* STM32_ACTIVATE_PLLI2S */
 
 #if STM32_ACTIVATE_PLLSAI
   /* PLLSAI activation.*/
-  RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ;
-  RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
+  RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ |
+                    STM32_PLLSAIP;
+  
   RCC->CR |= RCC_CR_PLLSAION;
 
   /* Waiting for PLL lock.*/
   while (!(RCC->CR & RCC_CR_PLLSAIRDY))
     ;
-#endif
+#endif /* STM32_ACTIVATE_PLLSAI */
 
   /* Other clock-related settings (dividers, MCO etc).*/
   RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
               STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
               STM32_HPRE;
 
+#if defined(STM32F446xx)
+  /* DCKCFGR register initialization, note, must take care of the _OFF
+   pseudo settings.*/
+  {
+    uint32_t dckcfgr = 0;
+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+    dckcfgr |= STM32_SAI2SEL;
+#endif
+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+    dckcfgr |= STM32_SAI1SEL;
+#endif
+#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
+    dckcfgr |= STM32_PLLSAIDIVR;
+#endif
+    RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;
+  }
+  RCC->DCKCFGR2 = STM32_CK48MSEL;
+#elif defined(STM32F469xx) || defined(STM32F479xx)
+  /* DCKCFGR register initialization, note, must take care of the _OFF
+   pseudo settings.*/
+  {
+    uint32_t dckcfgr = 0;
+  #if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+    dckcfgr |= STM32_SAI2SEL;
+  #endif
+  #if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+    dckcfgr |= STM32_SAI1SEL;
+  #endif
+  #if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
+    dckcfgr |= STM32_PLLSAIDIVR;
+  #endif
+    RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ | 
+                   STM32_CK48MSEL;
+  }
+#endif
+
   /* Flash setup.*/
 #if !defined(STM32_REMOVE_REVISION_A_FIX)
   /* Some old revisions of F4x MCUs randomly crashes with compiler