diff options
Diffstat (limited to 'os/hal/ports/STM32/LLD')
-rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/fsmc.c | 35 | ||||
-rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/fsmc.h | 4 | ||||
-rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c | 72 | ||||
-rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h | 20 |
4 files changed, 42 insertions, 89 deletions
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c index 8d821dca6..75d4af1a0 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c @@ -106,9 +106,9 @@ void fsmc_start(FSMCDriver *fsmcp) { if (&FSMCD1 == fsmcp) { rccResetFSMC(); rccEnableFSMC(FALSE); - #if STM32_NAND_USE_FSMC_INT - nvicEnableVector(FSMC_IRQn, STM32_FSMC_FSMC1_IRQ_PRIORITY); - #endif +#if !STM32_NAND_USE_EXT_INT + nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); +#endif } #endif /* STM32_FSMC_USE_FSMC1 */ @@ -132,50 +132,39 @@ void fsmc_stop(FSMCDriver *fsmcp) { /* Disables the peripheral.*/ #if STM32_FSMC_USE_FSMC1 if (&FSMCD1 == fsmcp) { - #if STM32_NAND_USE_FSMC_INT - nvicDisableVector(FSMC_IRQn); - #endif +#if !STM32_NAND_USE_EXT_INT + nvicDisableVector(STM32_FSMC_NUMBER); +#endif rccDisableFSMC(FALSE); } -#endif /* PLATFORM_STM32_USE_FSMC1 */ +#endif /* STM32_FSMC_USE_FSMC1 */ fsmcp->state = FSMC_STOP; } } -#if STM32_NAND_USE_FSMC_INT -/** - * @brief Serve common interrupt. - * - * @notapi - */ -void fsmc_serve_interrupt(void) { - - osalSysHalt("Unrealized"); -} - +#if !STM32_NAND_USE_EXT_INT /** * @brief FSMC shared interrupt handler. * * @notapi */ -CH_IRQ_HANDLER(FSMC_IRQHandler) { - osalSysHalt("This functionality untested"); +CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_PROLOGUE(); #if STM32_NAND_USE_FSMC_NAND1 if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK){ - NANDD1.isr_handler(&NANDD1, FSMCD1.nand1->SR); + NANDD1.isr_handler(&NANDD1); } #endif #if STM32_NAND_USE_FSMC_NAND2 if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK){ - NANDD2.isr_handler(&NANDD2, FSMCD1.nand2->SR); + NANDD2.isr_handler(&NANDD2); } #endif CH_IRQ_EPILOGUE(); } -#endif /* STM32_FSMC_USE_INT */ +#endif /* !STM32_NAND_USE_EXT_INT */ #endif /* HAL_USE_FSMC */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h index 0ab887b65..6896352a4 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h @@ -158,8 +158,8 @@ typedef struct { * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC. * You have to use EXTI module instead to workaround this issue. */ -#if !defined(STM32_NAND_USE_FSMC_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_FSMC_INT FALSE +#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__) +#define STM32_NAND_USE_EXT_INT FALSE #endif /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c index b37ff2697..d0cf573dc 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c @@ -87,7 +87,6 @@ static void wakeup_isr(NANDDriver *nandp){ */ static void nand_lld_suspend_thread(NANDDriver *nandp) { - //nandp->thread = chThdGetSelfX(); osalThreadSuspendS(&nandp->thread); } @@ -114,86 +113,60 @@ static uint32_t calc_eccps(NANDDriver *nandp){ /* Driver interrupt handlers. */ /*===========================================================================*/ -#if STM32_NAND_USE_FSMC_INT /** - * @brief Enable interrupts from FSMC + * @brief Enable interrupts from NAND * * @param[in] nandp pointer to the @p NANDDriver object * * @notapi */ static void nand_ready_isr_enable(NANDDriver *nandp) { +#if STM32_NAND_USE_EXT_INT + nandp->config->ext_nand_isr_enable(); +#else + nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | + FSMC_SR_ILEN | FSMC_SR_IFEN); nandp->nand->SR |= FSMC_SR_IREN; - osalSysHalt("Function untested"); +#endif } /** - * @brief Disable interrupts from FSMC + * @brief Disable interrupts from NAND * * @param[in] nandp pointer to the @p NANDDriver object * * @notapi */ static void nand_ready_isr_disable(NANDDriver *nandp) { +#if STM32_NAND_USE_EXT_INT + nandp->config->ext_nand_isr_disable(); +#else nandp->nand->SR &= ~FSMC_SR_IREN; - osalSysHalt("Function untested"); +#endif } /** * @brief Ready interrupt handler * * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] flags flags passed from FSMC intrrupt handler - * - * @notapi - */ -static void nand_isr_handler (NANDDriver *nandp, - nandflags_t flags){ - (void)nandp; - (void)flags; - - osalSysHalt("Unrealized"); -} -#else /* STM32_NAND_USE_FSMC_INT */ -/** - * @brief Disable interrupts from EXTI - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_enable(NANDDriver *nandp) { - nandp->config->ext_isr_enable(); -} - -/** - * @brief Enable interrupts from EXTI - * - * @param[in] nandp pointer to the @p NANDDriver object * * @notapi */ -static void nand_ready_isr_disable(NANDDriver *nandp) { - nandp->config->ext_isr_disable(); -} - -/** - * @brief Ready pin interrupt handler. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_isr_handler(NANDDriver *nandp){ +static void nand_isr_handler (NANDDriver *nandp){ osalSysLockFromISR(); +#if !STM32_NAND_USE_EXT_INT + osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ + nandp->nand->SR &= ~FSMC_SR_IRS; +#endif + switch (nandp->state){ case NAND_READ: nandp->state = NAND_DMA_RX; dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata, nandp->datalen); - /* thread will be woked up from DMA ISR */ + /* thread will be waked up from DMA ISR */ break; case NAND_ERASE: @@ -212,21 +185,18 @@ static void nand_isr_handler(NANDDriver *nandp){ osalSysHalt("Unhandled case"); break; } - osalSysUnlockFromISR(); } -#endif /* STM32_NAND_USE_FSMC_INT */ /** * @brief DMA RX end IRQ handler. * * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] flags pre-shifted content of the ISR register + * @param[in] flags pre-shifted content of the ISR register * * @notapi */ -static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, - uint32_t flags) { +static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { /* DMA errors handling.*/ #if defined(STM32_NAND_DMA_ERROR_HOOK) if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h index 0954a782f..6222caa3f 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h @@ -128,7 +128,7 @@ #error "FSMC not present in the selected device" #endif -#if !STM32_NAND_USE_FSMC_INT && !HAL_USE_EXT +#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT #error "External interrupt controller must be enabled to use this feature" #endif @@ -156,23 +156,17 @@ typedef uint32_t nandflags_t; */ typedef struct NANDDriver NANDDriver; -#if STM32_NAND_USE_FSMC_INT -/** - * @brief Type of interrupt handler function - */ -typedef void (*nandisrhandler_t) - (NANDDriver *nandp, nandflags_t flags); -#else /** * @brief Type of interrupt handler function */ typedef void (*nandisrhandler_t)(NANDDriver *nandp); +#if STM32_NAND_USE_EXT_INT /** * @brief Type of function switching external interrupts on and off. */ typedef void (*nandisrswitch_t)(void); -#endif /* STM32_NAND_USE_FSMC_INT */ +#endif /* STM32_NAND_USE_EXT_INT */ /** * @brief Driver configuration structure. @@ -224,16 +218,16 @@ typedef struct { * from STMicroelectronics. */ uint32_t pmem; -#if !STM32_NAND_USE_FSMC_INT +#if STM32_NAND_USE_EXT_INT /** * @brief Function enabling interrupts from EXTI */ - nandisrswitch_t ext_isr_enable; + nandisrswitch_t ext_nand_isr_enable; /** * @brief Function disabling interrupts from EXTI */ - nandisrswitch_t ext_isr_disable; -#endif /* !STM32_NAND_USE_FSMC_INT */ + nandisrswitch_t ext_nand_isr_disable; +#endif /* STM32_NAND_USE_EXT_INT */ } NANDConfig; /** |