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Diffstat (limited to 'os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h')
-rw-r--r--os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
index 07ca48f66..59f0cc1df 100644
--- a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
+++ b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
@@ -66,6 +66,14 @@
#endif
/**
+ * @brief Enable clock bypass.
+ * @note Allow clock speed up to 50 Mhz.
+ */
+#if !defined(STM32_SDC_SDMMC_50MHZ) || defined(__DOXYGEN__)
+#define STM32_SDC_SDMMC_50MHZ FALSE
+#endif
+
+/**
* @brief Write timeout in milliseconds.
*/
#if !defined(STM32_SDC_SDMMC_WRITE_TIMEOUT) || defined(__DOXYGEN__)
@@ -190,6 +198,10 @@
#error "STM32_SDMMC2CLK must not exceed 48MHz"
#endif
+#if defined(STM32_SDC_SDMMC_50MHZ) && STM32_SDC_SDMMC_50MHZ && !defined(STM32F7XX)
+#error "50 Mhz clock only works for STM32F7XX"
+#endif
+
/* SDMMC IRQ priority tests.*/
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SDC_SDMMC1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SDMMC1"