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path: root/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
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Diffstat (limited to 'os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c')
-rw-r--r--os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
index 84f0be664..1acd4e5f1 100644
--- a/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
+++ b/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
@@ -206,7 +206,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
iopadid_t pad,
ioeventmode_t mode) {
- uint32_t padmask, cridx, crmask, portidx;
+ uint32_t padmask, cridx, croff, crmask, portidx;
/* Mask of the pad.*/
padmask = 1U << (uint32_t)pad;
@@ -219,14 +219,15 @@ void _pal_lld_enablepadevent(ioportid_t port,
/* Index and mask of the SYSCFG CR register to be used.*/
cridx = (uint32_t)pad >> 2U;
- crmask = ~(0xFU << (((uint32_t)pad & 3U) * 4U));
+ croff = ((uint32_t)pad & 3U) * 4U;
+ crmask = ~(0xFU << croff);
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = (uint32_t)port >> 10U;
+ portidx = ((uint32_t)port >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
- AFIO->EXTICR[cridx] = (AFIO->EXTICR[cridx] & crmask) | portidx;
+ AFIO->EXTICR[cridx] = (AFIO->EXTICR[cridx] & crmask) | (portidx << croff);
/* Programming edge registers.*/
if (mode & PAL_EVENT_MODE_RISING_EDGE)
@@ -245,7 +246,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
/**
* @brief Pad event disable.
- * @details This function also disables previously programmed event callbacks.
+ * @details This function disables previously programmed event callbacks.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
@@ -271,7 +272,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = (uint32_t)port >> 10U;
+ portidx = ((uint32_t)port >> 10U) & 0xFU;
crport = (AFIO->EXTICR[cridx] >> croff) & 0xFU;
@@ -283,12 +284,12 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
EXTI->RTSR = rtsr1 & ~padmask;
EXTI->FTSR = ftsr1 & ~padmask;
EXTI->PR = padmask;
- }
#if PAL_USE_CALLBACKS || PAL_USE_WAIT
/* Callback cleared and/or thread reset.*/
_pal_clear_event(pad);
#endif
+ }
}
#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */