diff options
Diffstat (limited to 'os/hal/ports/STM32/LLD/DMAv3')
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c | 170 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h | 114 |
2 files changed, 146 insertions, 138 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c index eefebb8ee..180dd4b7b 100644 --- a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c @@ -40,12 +40,12 @@ /*===========================================================================*/
/**
- * @brief Mask of the DMA1 streams in @p dma_streams_mask.
+ * @brief Mask of the DMA1 streams in @p dma.streams_mask.
*/
#define STM32_DMA1_STREAMS_MASK 0x000000FFU
/**
- * @brief Mask of the DMA2 streams in @p dma_streams_mask.
+ * @brief Mask of the DMA2 streams in @p dma.streams_mask.
*/
#define STM32_DMA2_STREAMS_MASK 0x0000FF00U
@@ -61,22 +61,22 @@ * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
- {DMA1_Stream0, &DMA1->LIFCR, 0, DMAMUX1_Channel0, 0, STM32_DMA1_CH0_NUMBER},
- {DMA1_Stream1, &DMA1->LIFCR, 6, DMAMUX1_Channel1, 1, STM32_DMA1_CH1_NUMBER},
- {DMA1_Stream2, &DMA1->LIFCR, 16, DMAMUX1_Channel2, 2, STM32_DMA1_CH2_NUMBER},
- {DMA1_Stream3, &DMA1->LIFCR, 22, DMAMUX1_Channel3, 3, STM32_DMA1_CH3_NUMBER},
- {DMA1_Stream4, &DMA1->HIFCR, 0, DMAMUX1_Channel4, 4, STM32_DMA1_CH4_NUMBER},
- {DMA1_Stream5, &DMA1->HIFCR, 6, DMAMUX1_Channel5, 5, STM32_DMA1_CH5_NUMBER},
- {DMA1_Stream6, &DMA1->HIFCR, 16, DMAMUX1_Channel6, 6, STM32_DMA1_CH6_NUMBER},
- {DMA1_Stream7, &DMA1->HIFCR, 22, DMAMUX1_Channel7, 7, STM32_DMA1_CH7_NUMBER},
- {DMA2_Stream0, &DMA2->LIFCR, 0, DMAMUX1_Channel8, 8, STM32_DMA2_CH0_NUMBER},
- {DMA2_Stream1, &DMA2->LIFCR, 6, DMAMUX1_Channel9, 9, STM32_DMA2_CH1_NUMBER},
+ {DMA1_Stream0, &DMA1->LIFCR, 0, DMAMUX1_Channel0, 0, STM32_DMA1_CH0_NUMBER},
+ {DMA1_Stream1, &DMA1->LIFCR, 6, DMAMUX1_Channel1, 1, STM32_DMA1_CH1_NUMBER},
+ {DMA1_Stream2, &DMA1->LIFCR, 16, DMAMUX1_Channel2, 2, STM32_DMA1_CH2_NUMBER},
+ {DMA1_Stream3, &DMA1->LIFCR, 22, DMAMUX1_Channel3, 3, STM32_DMA1_CH3_NUMBER},
+ {DMA1_Stream4, &DMA1->HIFCR, 0, DMAMUX1_Channel4, 4, STM32_DMA1_CH4_NUMBER},
+ {DMA1_Stream5, &DMA1->HIFCR, 6, DMAMUX1_Channel5, 5, STM32_DMA1_CH5_NUMBER},
+ {DMA1_Stream6, &DMA1->HIFCR, 16, DMAMUX1_Channel6, 6, STM32_DMA1_CH6_NUMBER},
+ {DMA1_Stream7, &DMA1->HIFCR, 22, DMAMUX1_Channel7, 7, STM32_DMA1_CH7_NUMBER},
+ {DMA2_Stream0, &DMA2->LIFCR, 0, DMAMUX1_Channel8, 8, STM32_DMA2_CH0_NUMBER},
+ {DMA2_Stream1, &DMA2->LIFCR, 6, DMAMUX1_Channel9, 9, STM32_DMA2_CH1_NUMBER},
{DMA2_Stream2, &DMA2->LIFCR, 16, DMAMUX1_Channel10, 10, STM32_DMA2_CH2_NUMBER},
{DMA2_Stream3, &DMA2->LIFCR, 22, DMAMUX1_Channel11, 11, STM32_DMA2_CH3_NUMBER},
- {DMA2_Stream4, &DMA2->HIFCR, 0, DMAMUX1_Channel12, 12, STM32_DMA2_CH4_NUMBER},
- {DMA2_Stream5, &DMA2->HIFCR, 6, DMAMUX1_Channel13, 13, STM32_DMA2_CH5_NUMBER},
+ {DMA2_Stream4, &DMA2->HIFCR, 0, DMAMUX1_Channel12, 12, STM32_DMA2_CH4_NUMBER},
+ {DMA2_Stream5, &DMA2->HIFCR, 6, DMAMUX1_Channel13, 13, STM32_DMA2_CH5_NUMBER},
{DMA2_Stream6, &DMA2->HIFCR, 16, DMAMUX1_Channel14, 14, STM32_DMA2_CH6_NUMBER},
- {DMA2_Stream7, &DMA2->HIFCR, 22, DMAMUX1_Channel15, 15, STM32_DMA2_CH7_NUMBER},
+ {DMA2_Stream7, &DMA2->HIFCR, 22, DMAMUX1_Channel15, 15, STM32_DMA2_CH7_NUMBER}
};
/*===========================================================================*/
@@ -92,14 +92,18 @@ typedef struct { } dma_isr_redir_t;
/**
- * @brief Mask of the allocated streams.
+ * @brief DMA driver base structure.
*/
-static uint32_t dma_streams_mask;
-
-/**
- * @brief DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+static struct {
+ /**
+ * @brief Mask of the allocated streams.
+ */
+ uint32_t streams_mask;
+ /**
+ * @brief DMA IRQ redirectors.
+ */
+ dma_isr_redir_t isr_redir[STM32_DMA_STREAMS];
+} dma;
/*===========================================================================*/
/* Driver local functions. */
@@ -121,8 +125,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH0_HANDLER) { flags = (DMA1->LISR >> 0U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 0U;
- if (dma_isr_redir[0].func)
- dma_isr_redir[0].func(dma_isr_redir[0].param, flags);
+ if (dma.isr_redir[0].func)
+ dma.isr_redir[0].func(dma.isr_redir[0].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -139,8 +143,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) { flags = (DMA1->LISR >> 6U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 6U;
- if (dma_isr_redir[1].func)
- dma_isr_redir[1].func(dma_isr_redir[1].param, flags);
+ if (dma.isr_redir[1].func)
+ dma.isr_redir[1].func(dma.isr_redir[1].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -157,8 +161,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) { flags = (DMA1->LISR >> 16U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 16U;
- if (dma_isr_redir[2].func)
- dma_isr_redir[2].func(dma_isr_redir[2].param, flags);
+ if (dma.isr_redir[2].func)
+ dma.isr_redir[2].func(dma.isr_redir[2].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -175,8 +179,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) { flags = (DMA1->LISR >> 22U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 22U;
- if (dma_isr_redir[3].func)
- dma_isr_redir[3].func(dma_isr_redir[3].param, flags);
+ if (dma.isr_redir[3].func)
+ dma.isr_redir[3].func(dma.isr_redir[3].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -193,8 +197,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) { flags = (DMA1->HISR >> 0U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 0U;
- if (dma_isr_redir[4].func)
- dma_isr_redir[4].func(dma_isr_redir[4].param, flags);
+ if (dma.isr_redir[4].func)
+ dma.isr_redir[4].func(dma.isr_redir[4].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -211,8 +215,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) { flags = (DMA1->HISR >> 6U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 6U;
- if (dma_isr_redir[5].func)
- dma_isr_redir[5].func(dma_isr_redir[5].param, flags);
+ if (dma.isr_redir[5].func)
+ dma.isr_redir[5].func(dma.isr_redir[5].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -229,8 +233,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) { flags = (DMA1->HISR >> 16U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 16U;
- if (dma_isr_redir[6].func)
- dma_isr_redir[6].func(dma_isr_redir[6].param, flags);
+ if (dma.isr_redir[6].func)
+ dma.isr_redir[6].func(dma.isr_redir[6].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -247,8 +251,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) { flags = (DMA1->HISR >> 22U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 22U;
- if (dma_isr_redir[7].func)
- dma_isr_redir[7].func(dma_isr_redir[7].param, flags);
+ if (dma.isr_redir[7].func)
+ dma.isr_redir[7].func(dma.isr_redir[7].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -265,8 +269,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH0_HANDLER) { flags = (DMA2->LISR >> 0U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 0U;
- if (dma_isr_redir[8].func)
- dma_isr_redir[8].func(dma_isr_redir[8].param, flags);
+ if (dma.isr_redir[8].func)
+ dma.isr_redir[8].func(dma.isr_redir[8].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -283,8 +287,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) { flags = (DMA2->LISR >> 6U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 6U;
- if (dma_isr_redir[9].func)
- dma_isr_redir[9].func(dma_isr_redir[9].param, flags);
+ if (dma.isr_redir[9].func)
+ dma.isr_redir[9].func(dma.isr_redir[9].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -301,8 +305,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) { flags = (DMA2->LISR >> 16U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 16U;
- if (dma_isr_redir[10].func)
- dma_isr_redir[10].func(dma_isr_redir[10].param, flags);
+ if (dma.isr_redir[10].func)
+ dma.isr_redir[10].func(dma.isr_redir[10].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -319,8 +323,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) { flags = (DMA2->LISR >> 22U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 22U;
- if (dma_isr_redir[11].func)
- dma_isr_redir[11].func(dma_isr_redir[11].param, flags);
+ if (dma.isr_redir[11].func)
+ dma.isr_redir[11].func(dma.isr_redir[11].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -337,8 +341,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) { flags = (DMA2->HISR >> 0U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 0U;
- if (dma_isr_redir[12].func)
- dma_isr_redir[12].func(dma_isr_redir[12].param, flags);
+ if (dma.isr_redir[12].func)
+ dma.isr_redir[12].func(dma.isr_redir[12].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -355,8 +359,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) { flags = (DMA2->HISR >> 6U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 6U;
- if (dma_isr_redir[13].func)
- dma_isr_redir[13].func(dma_isr_redir[13].param, flags);
+ if (dma.isr_redir[13].func)
+ dma.isr_redir[13].func(dma.isr_redir[13].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -373,8 +377,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) { flags = (DMA2->HISR >> 16U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 16U;
- if (dma_isr_redir[14].func)
- dma_isr_redir[14].func(dma_isr_redir[14].param, flags);
+ if (dma.isr_redir[14].func)
+ dma.isr_redir[14].func(dma.isr_redir[14].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -391,8 +395,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) { flags = (DMA2->HISR >> 22U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 22U;
- if (dma_isr_redir[15].func)
- dma_isr_redir[15].func(dma_isr_redir[15].param, flags);
+ if (dma.isr_redir[15].func)
+ dma.isr_redir[15].func(dma.isr_redir[15].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -409,10 +413,11 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) { void dmaInit(void) {
unsigned i;
- dma_streams_mask = 0U;
+ dma.streams_mask = 0U;
for (i = 0U; i < STM32_DMA_STREAMS; i++) {
_stm32_dma_streams[i].stream->CR = 0U;
- dma_isr_redir[i].func = NULL;
+ dma.isr_redir[i].func = NULL;
+ dma.isr_redir[i].param = NULL;
}
DMA1->LIFCR = 0xFFFFFFFFU;
DMA1->HIFCR = 0xFFFFFFFFU;
@@ -434,7 +439,7 @@ void dmaInit(void) { * @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] priority IRQ priority for the DMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
@@ -444,58 +449,57 @@ void dmaInit(void) { *
* @special
*/
-bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+bool dmaStreamAllocate(const stm32_dma_stream_t *stp,
uint32_t priority,
stm32_dmaisr_t func,
void *param) {
- osalDbgCheck(dmastp != NULL);
+ osalDbgCheck(stp != NULL);
/* Checks if the stream is already taken.*/
- if ((dma_streams_mask & (1U << dmastp->selfindex)) != 0U)
+ if ((dma.streams_mask & (1U << stp->selfindex)) != 0U)
return true;
/* Marks the stream as allocated.*/
- dma_isr_redir[dmastp->selfindex].func = func;
- dma_isr_redir[dmastp->selfindex].param = param;
- dma_streams_mask |= (1U << dmastp->selfindex);
+ dma.isr_redir[stp->selfindex].func = func;
+ dma.isr_redir[stp->selfindex].param = param;
+ dma.streams_mask |= (1U << stp->selfindex);
/* Enabling DMA clocks required by the current streams set.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) {
+ if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) {
rccEnableDMA1(false);
}
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) {
+ if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) {
rccEnableDMA2(false);
}
/* Putting the stream in a safe state.*/
- dmaStreamDisable(dmastp);
- dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
- dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
+ dmaStreamDisable(stp);
+ stp->stream->CR = STM32_DMA_CR_RESET_VALUE;
+ stp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
/* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL) {
- nvicEnableVector(dmastp->vector, priority);
+ nvicEnableVector(stp->vector, priority);
}
return false;
}
-
/**
* @brief Associates a peripheral request to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] per peripheral identifier
*
* @special
*/
-void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per) {
+void dmaSetRequestSource(const stm32_dma_stream_t *stp, uint32_t per) {
osalDbgCheck(per < 256U);
- dmastp->mux->CCR = per;
+ stp->mux->CCR = per;
}
/**
@@ -507,29 +511,33 @@ void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per) { * @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
*
* @special
*/
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+void dmaStreamRelease(const stm32_dma_stream_t *stp) {
- osalDbgCheck(dmastp != NULL);
+ osalDbgCheck(stp != NULL);
/* Check if the streams is not taken.*/
- osalDbgAssert((dma_streams_mask & (1U << dmastp->selfindex)) != 0U,
+ osalDbgAssert((dma.streams_mask & (1U << stp->selfindex)) != 0U,
"not allocated");
/* Disables the associated IRQ vector.*/
- nvicDisableVector(dmastp->vector);
+ nvicDisableVector(stp->vector);
/* Marks the stream as not allocated.*/
- dma_streams_mask &= ~(1U << dmastp->selfindex);
+ dma.streams_mask &= ~(1U << stp->selfindex);
+
+ /* Clearing associated handler and parameter.*/
+ dma.isr_redir->func = NULL;
+ dma.isr_redir->param = NULL;
/* Shutting down clocks that are no more required, if any.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
+ if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
rccDisableDMA1();
}
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
+ if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
rccDisableDMA2();
}
}
diff --git a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h index 8aa640deb..ff9e19538 100644 --- a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h @@ -44,8 +44,8 @@ /**
* @brief Checks if a DMA priority is within the valid range.
- * @param[in] prio DMA priority
*
+ * @param[in] prio DMA priority
* @retval The check result.
* @retval FALSE invalid DMA priority.
* @retval TRUE correct DMA priority.
@@ -54,8 +54,8 @@ /**
* @brief Checks if a DMA channel is within the valid range.
- * @param[in] ch DMA channel
*
+ * @param[in] ch DMA channel
* @retval The check result.
* @retval FALSE invalid DMA channel.
* @retval TRUE correct DMA channel.
@@ -67,7 +67,7 @@ * @{
*/
/**
- * @brief Returns a pointer to a stm32_dma_stream_t structure.
+ * @brief Returns a pointer to a @p stm32_dma_stream_t structure.
*
* @param[in] id the stream numeric identifier
* @return A pointer to the stm32_dma_stream_t constant structure
@@ -416,13 +416,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] addr value to be written in the PAR register
*
* @special
*/
-#define dmaStreamSetPeripheral(dmastp, addr) { \
- (dmastp)->stream->PAR = (uint32_t)(addr); \
+#define dmaStreamSetPeripheral(stp, addr) { \
+ (stp)->stream->PAR = (uint32_t)(addr); \
}
/**
@@ -431,26 +431,26 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] addr value to be written in the M0AR register
*
* @special
*/
-#define dmaStreamSetMemory0(dmastp, addr) { \
- (dmastp)->stream->M0AR = (uint32_t)(addr); \
+#define dmaStreamSetMemory0(stp, addr) { \
+ (stp)->stream->M0AR = (uint32_t)(addr); \
}
/**
* @brief Associates an alternate memory destination to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] addr value to be written in the M1AR register
*
* @special
*/
-#define dmaStreamSetMemory1(dmastp, addr) { \
- (dmastp)->stream->M1AR = (uint32_t)(addr); \
+#define dmaStreamSetMemory1(stp, addr) { \
+ (stp)->stream->M1AR = (uint32_t)(addr); \
}
/**
@@ -459,13 +459,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] size value to be written in the CNDTR register
*
* @special
*/
-#define dmaStreamSetTransactionSize(dmastp, size) { \
- (dmastp)->stream->NDTR = (uint32_t)(size); \
+#define dmaStreamSetTransactionSize(stp, size) { \
+ (stp)->stream->NDTR = (uint32_t)(size); \
}
/**
@@ -474,12 +474,12 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @return The number of transfers to be performed.
*
* @special
*/
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))
+#define dmaStreamGetTransactionSize(stp) ((size_t)((stp)->stream->NDTR))
/**
* @brief Programs the stream mode settings.
@@ -487,13 +487,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] mode value to be written in the CR register
*
* @special
*/
-#define dmaStreamSetMode(dmastp, mode) { \
- (dmastp)->stream->CR = (uint32_t)(mode); \
+#define dmaStreamSetMode(stp, mode) { \
+ (stp)->stream->CR = (uint32_t)(mode); \
}
/**
@@ -502,13 +502,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] mode value to be written in the FCR register
*
* @special
*/
-#define dmaStreamSetFIFO(dmastp, mode) { \
- (dmastp)->stream->FCR = (uint32_t)(mode); \
+#define dmaStreamSetFIFO(stp, mode) { \
+ (stp)->stream->FCR = (uint32_t)(mode); \
}
/**
@@ -517,12 +517,12 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
*
* @special
*/
-#define dmaStreamEnable(dmastp) { \
- (dmastp)->stream->CR |= STM32_DMA_CR_EN; \
+#define dmaStreamEnable(stp) { \
+ (stp)->stream->CR |= STM32_DMA_CR_EN; \
}
/**
@@ -535,17 +535,17 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
*
* @special
*/
-#define dmaStreamDisable(dmastp) { \
- (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
- STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \
- STM32_DMA_CR_EN); \
- while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \
+#define dmaStreamDisable(stp) { \
+ (stp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \
+ STM32_DMA_CR_EN); \
+ while (((stp)->stream->CR & STM32_DMA_CR_EN) != 0) \
; \
- dmaStreamClearInterrupt(dmastp); \
+ dmaStreamClearInterrupt(stp); \
}
/**
@@ -554,12 +554,12 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
*
* @special
*/
-#define dmaStreamClearInterrupt(dmastp) { \
- *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
+#define dmaStreamClearInterrupt(stp) { \
+ *(stp)->ifcr = STM32_DMA_ISR_MASK << (stp)->ishift; \
}
/**
@@ -569,7 +569,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @param[in] mode value to be written in the CCR register, this value
* is implicitly ORed with:
* - @p STM32_DMA_CR_MINC
@@ -581,14 +581,14 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @param[in] dst destination address
* @param[in] n number of data units to copy
*/
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
- dmaStreamSetPeripheral(dmastp, src); \
- dmaStreamSetMemory0(dmastp, dst); \
- dmaStreamSetTransactionSize(dmastp, n); \
- dmaStreamSetMode(dmastp, (mode) | \
- STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
- STM32_DMA_CR_DIR_M2M); \
- dmaStreamEnable(dmastp); \
+#define dmaStartMemCopy(stp, mode, src, dst, n) { \
+ dmaStreamSetPeripheral(stp, src); \
+ dmaStreamSetMemory0(stp, dst); \
+ dmaStreamSetTransactionSize(stp, n); \
+ dmaStreamSetMode(stp, (mode) | \
+ STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
+ STM32_DMA_CR_DIR_M2M); \
+ dmaStreamEnable(stp); \
}
/**
@@ -596,14 +596,14 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
*/
-#define dmaWaitCompletion(dmastp) { \
- (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
- STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE); \
- while ((dmastp)->stream->CR & STM32_DMA_CR_EN) \
+#define dmaWaitCompletion(stp) { \
+ (stp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE); \
+ while ((stp)->stream->CR & STM32_DMA_CR_EN) \
; \
- dmaStreamClearInterrupt(dmastp); \
+ dmaStreamClearInterrupt(stp); \
}
/**
@@ -612,13 +612,13 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
+ * @param[in] stp pointer to a @p stm32_dma_stream_t structure
* @return Current memory target index.
*
* @special
*/
-#define dmaStreamGetCurrentTarget(dmastp) \
- (((dmastp)->stream->CR >> DMA_SxCR_CT_Pos) & 1U)
+#define dmaStreamGetCurrentTarget(stp) \
+ (((stp)->stream->CR >> DMA_SxCR_CT_Pos) & 1U)
/** @} */
/*===========================================================================*/
@@ -633,12 +633,12 @@ extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; extern "C" {
#endif
void dmaInit(void);
- bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+ bool dmaStreamAllocate(const stm32_dma_stream_t *stp,
uint32_t priority,
stm32_dmaisr_t func,
void *param);
- void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per);
- void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+ void dmaSetRequestSource(const stm32_dma_stream_t *stp, uint32_t per);
+ void dmaStreamRelease(const stm32_dma_stream_t *stp);
#ifdef __cplusplus
}
#endif
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