diff options
Diffstat (limited to 'os/hal/ports/STM32/LLD/DMAv2')
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c | 19 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h | 23 |
2 files changed, 42 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c index 9e8d31bc8..072519e6f 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c @@ -428,6 +428,25 @@ void dmaInit(void) { DMA1->HIFCR = 0xFFFFFFFFU;
DMA2->LIFCR = 0xFFFFFFFFU;
DMA2->HIFCR = 0xFFFFFFFFU;
+
+#if defined(STM32F7XX)
+ /* If the DMA is in use then the DMA-accessible RAM must be programmed as
+ Write Through using the MPU, region zero is used with a size of 512kB,
+ the sub-regions are programmed as follow:
+ - 0..4, enabled, it is the normal, DMA-accessible, RAM.
+ - 5..7, disabled, beyond RAM area.
+ The system memory layout is used as "background" for the MPU regions.*/
+ mpuConfigureRegion(MPU_REGION_0,
+ 0x20000000U,
+ MPU_RASR_ATTR_AP_RW_RW |
+ MPU_RASR_ATTR_CACHEABLE_WT_NWA |
+ MPU_RNR_REGION(5) |
+ MPU_RNR_REGION(6) |
+ MPU_RNR_REGION(7) |
+ MPU_RASR_SIZE_512K |
+ MPU_RASR_ENABLE);
+ mpuEnable(MPU_CTRL_PRIVDEFENA);
+#endif
}
/**
diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h index 2c05ba470..e20ebe637 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h @@ -235,6 +235,29 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /* Driver macros. */
/*===========================================================================*/
+#if defined(STM32F7XX) || defined(__DOXYGEN__)
+/**
+ * @brief Invalidates the data cache lines overlapping a DMA buffer.
+ * @note On devices without data cache this function does nothing.
+ * @note The function takes care of cache lines alignment.
+ *
+ * @param[in] addr address of the DMA buffer
+ * @param[in] size size of the DMA buffer
+ *
+ * @api
+ */
+#define dmaBufferInvalidate(addr, size) { \
+ uint32_t *aaddr = (uint32_t *)(((uint32_t)(addr)) & ~0x1FU); \
+ uint32_t asize = (uint32_t)((((size) - 1) | 0x1FU) + 1U); \
+ SCB_CleanInvalidateDCache_by_Addr(aaddr, asize); \
+}
+#else
+#define dmaBufferInvalidate(addr, size) { \
+ (void)(addr); \
+ (void)(size); \
+}
+#endif
+
/**
* @name Macro Functions
* @{
|