diff options
Diffstat (limited to 'os/hal/ports/STM32/LLD/DMAv2')
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv2/notes.txt | 1 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h | 32 |
2 files changed, 33 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv2/notes.txt b/os/hal/ports/STM32/LLD/DMAv2/notes.txt index 28e2a7ce4..4c01d8309 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/notes.txt +++ b/os/hal/ports/STM32/LLD/DMAv2/notes.txt @@ -5,6 +5,7 @@ Driver capability: - The driver supports the STM32 enhanced DMA controller found on F2, F4 and
F7 sub-families.
- Support for automatic the channel selection.
+- Support for cache flushing and invalidation.
The file registry must export:
diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h index 49139f831..fdc76ee59 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h @@ -240,6 +240,9 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #if defined(STM32F7XX) || defined(__DOXYGEN__)
/**
* @brief Invalidates the data cache lines overlapping a DMA buffer.
+ * @details This function is meant to make sure that data written in
+ * data cache is invalidated. It is used for DMA buffers that
+ * must have been written by a DMA stream.
* @note On devices without data cache this function does nothing.
* @note The function takes care of cache lines alignment.
*
@@ -253,6 +256,31 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); uint8_t *end = (uint8_t *)(((((uint32_t)(eaddr)) - 1U) | 0x1FU) + 1U); \
__DSB(); \
while (start < end) { \
+ SCB->DCIMVAC = (uint32_t)start; \
+ start += 32U; \
+ } \
+ __DSB(); \
+ __ISB(); \
+}
+
+/**
+ * @brief Flushes the data cache lines overlapping a DMA buffer.
+ * @details This function is meant to make sure that data written in
+ * data cache is flushed to RAM. It is used for DMA buffers that
+ * must be read by a DMA stream.
+ * @note On devices without data cache this function does nothing.
+ * @note The function takes care of cache lines alignment.
+ *
+ * @param[in] saddr start address of the DMA buffer, inclusive
+ * @param[in] eaddr end address of the DMA buffer, not inclusive
+ *
+ * @api
+ */
+#define dmaBufferFlush(saddr, eaddr) { \
+ uint8_t *start = (uint8_t *)(((uint32_t)(saddr)) & ~0x1FU); \
+ uint8_t *end = (uint8_t *)(((((uint32_t)(eaddr)) - 1U) | 0x1FU) + 1U); \
+ __DSB(); \
+ while (start < end) { \
SCB->DCCIMVAC = (uint32_t)start; \
start += 32U; \
} \
@@ -264,6 +292,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); (void)(addr); \
(void)(size); \
}
+#define dmaBufferFlush(addr, size) { \
+ (void)(addr); \
+ (void)(size); \
+}
#endif
/**
|