diff options
Diffstat (limited to 'os/hal/ports/STM32/LLD/DACv1/dac_lld.h')
| -rw-r--r-- | os/hal/ports/STM32/LLD/DACv1/dac_lld.h | 288 |
1 files changed, 145 insertions, 143 deletions
diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.h b/os/hal/ports/STM32/LLD/DACv1/dac_lld.h index 9cf6158c3..f63d64139 100644 --- a/os/hal/ports/STM32/LLD/DACv1/dac_lld.h +++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.h @@ -33,43 +33,6 @@ /* Driver constants. */
/*===========================================================================*/
-#define STM32_DAC_CR_EN DAC_CR_EN1
-#define STM32_DAC_CR_DMAEN DAC_CR_DMAEN1
-#define STM32_DAC_CR_TEN DAC_CR_TEN1
-
-#define STM32_DAC_CR_MASK (uint32_t)0x00000FFE
-
-#define STM32_DAC_CR_BOFF_ENABLE (uint32_t)0x00000000
-#define STM32_DAC_CR_BOFF_DISABLE DAC_CR_BOFF1
-
-#define STM32_DAC_CR_TSEL_NONE (uint32_t)0x00000000
-#define STM32_DAC_CR_TSEL_TIM2 DAC_CR_TEN1 | DAC_CR_TSEL1_2
-#define STM32_DAC_CR_TSEL_TIM4 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_2
-#define STM32_DAC_CR_TSEL_TIM5 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1
-#define STM32_DAC_CR_TSEL_TIM6 DAC_CR_TEN1
-#define STM32_DAC_CR_TSEL_TIM7 DAC_CR_TEN1 | DAC_CR_TSEL1_1
-#define STM32_DAC_CR_TSEL_TIM3 DAC_CR_TEN1 | DAC_CR_TSEL1_0
-#define STM32_DAC_CR_TSEL_TIM18 DAC_CR_TEN1 | DAC_CR_TSEL1_0 | DAC_CR_TSEL1_1
-#define STM32_DAC_CR_TSEL_EXT_IT9 DAC_CR_TEN1 | DAC_CR_TEN1 | DAC_CR_TSEL1_2
-#define STM32_DAC_CR_TSEL_SOFT DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_2
-
-#define STM32_DAC_CR_WAVE_NONE (uint32_t)0x00000000
-#define STM32_DAC_CR_WAVE_NOISE DAC_CR_WAVE1_0
-#define STM32_DAC_CR_WAVE_TRIANGLE DAC_CR_WAVE1_1
-
-#define STM32_DAC_MAMP_1 (uint32_t)0x00000000
-#define STM32_DAC_MAMP_3 DAC_CR_MAMP1_0
-#define STM32_DAC_MAMP_7 DAC_CR_MAMP1_1
-#define STM32_DAC_MAMP_15 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1
-#define STM32_DAC_MAMP_31 DAC_CR_MAMP1_2
-#define STM32_DAC_MAMP_63 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_2
-#define STM32_DAC_MAMP_127 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
-#define STM32_DAC_MAMP_255 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
-#define STM32_DAC_MAMP_511 DAC_CR_MAMP1_3
-#define STM32_DAC_MAMP_1023 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_3
-#define STM32_DAC_MAMP_2047 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_3
-#define STM32_DAC_MAMP_4095 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
-
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -79,122 +42,131 @@ * @{
*/
/**
- * @brief DAC CHN1 driver enable switch.
- * @details If set to @p TRUE the support for DAC CHN1 is included.
- * @note The default is @p TRUE.
+ * @brief Enables the DAC dual mode.
+ * @note In dual mode DAC second channels cannot be accessed individually.
*/
-#if !defined(STM32_DAC_USE_CHN1) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_CHN1 FALSE
+#if !defined(STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
+#define STM32_DAC_DUAL_MODE FALSE
#endif
/**
- * @brief DAC CHN2 driver enable switch.
- * @details If set to @p TRUE the support for DAC CHN2 is included.
- * @note The default is @p TRUE.
+ * @brief DAC1 CH1 driver enable switch.
+ * @details If set to @p TRUE the support for DAC1 channel 1 is included.
+ * @note The default is @p FALSE.
*/
-#if !defined(STM32_DAC_USE_CHN2) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_CHN2 FALSE
+#if !defined(STM32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_DAC1_CH1 FALSE
#endif
/**
- * @brief DAC CHN3 driver enable switch.
- * @details If set to @p TRUE the support for DAC CHN3 is included.
- * @note The default is @p TRUE.
+ * @brief DAC1 CH2 driver enable switch.
+ * @details If set to @p TRUE the support for DAC1 channel 2 is included.
+ * @note The default is @p FALSE.
*/
-#if !defined(STM32_DAC_USE_CHN3) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_CHN3 FALSE
+#if !defined(STM32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_DAC1_CH2 FALSE
#endif
/**
- * @brief DAC CHN1 interrupt priority level setting.
+ * @brief DAC2 CH1 driver enable switch.
+ * @details If set to @p TRUE the support for DAC2 channel 1 is included.
+ * @note The default is @p FALSE.
*/
-#if !defined(STM32_DAC_CHN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN1_IRQ_PRIORITY 10
+#if !defined(STM32_DAC_USE_DAC2_CH1) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_DAC2_CH1 FALSE
#endif
/**
- * @brief DAC CHN2 interrupt priority level setting.
+ * @brief DAC2 CH2 driver enable switch.
+ * @details If set to @p TRUE the support for DAC2 channel 2 is included.
+ * @note The default is @p FALSE.
*/
-#if !defined(STM32_DAC_CHN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN2_IRQ_PRIORITY 10
+#if !defined(STM32_DAC_USE_DAC2_CH2) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_DAC2_CH2 FALSE
#endif
/**
- * @brief DAC CHN3 interrupt priority level setting.
+ * @brief DAC1 CH1 interrupt priority level setting.
*/
-#if !defined(STM32_DAC_CHN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN3_IRQ_PRIORITY 10
+#if !defined(STM32_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC1_CH1_IRQ_PRIORITY 10
#endif
/**
- * @brief DAC CHN1 DMA priority (0..3|lowest..highest).
+ * @brief DAC1 CH2 interrupt priority level setting.
*/
-#if !defined(STM32_DAC_CHN1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN1_DMA_PRIORITY 2
+#if !defined(STM32_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC1_CH2_IRQ_PRIORITY 10
#endif
/**
- * @brief DAC CHN2 DMA priority (0..3|lowest..highest).
+ * @brief DAC2 CH1 interrupt priority level setting.
*/
-#if !defined(STM32_DAC_CHN2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN2_DMA_PRIORITY 2
+#if !defined(STM32_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC2_CH1_IRQ_PRIORITY 10
#endif
/**
- * @brief DAC CHN3 DMA priority (0..3|lowest..highest).
+ * @brief DAC2 CH2 interrupt priority level setting.
*/
-#if !defined(STM32_DAC_CHN3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN2_DMA_PRIORITY 2
+#if !defined(STM32_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC2_CH2_IRQ_PRIORITY 10
#endif
/**
- * @brief DAC DMA error hook.
+ * @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
*/
-#if !defined(STM32_DAC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_DAC_DMA_ERROR_HOOK(dacp) osalSysHalt()
+#if !defined(STM32_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC1_CH1_DMA_PRIORITY 2
#endif
/**
- * @brief DMA stream used for DAC CHN1 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
+ * @brief DAC1 CH2 DMA priority (0..3|lowest..highest).
*/
-#if !defined(STM32_DAC_CHN1_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#if !defined(STM32_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC1_CH2_DMA_PRIORITY 2
#endif
/**
- * @brief DMA stream used for DAC CHN2 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
+ * @brief DAC2 CH1 DMA priority (0..3|lowest..highest).
*/
-#if !defined(STM32_DAC_CHN2_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#if !defined(STM32_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC2_CH1_DMA_PRIORITY 2
#endif
/**
- * @brief DMA stream used for DAC CHN3 TX operations.
- * @note This option is only available on platforms with enhanced DMA.
+ * @brief DAC2 CH2 DMA priority (0..3|lowest..highest).
*/
-#if !defined(STM32_DAC_CHN3_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN3_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#if !defined(STM32_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC2_CH2_DMA_PRIORITY 2
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
-#if STM32_DAC_USE_CHN1 && !STM32_HAS_DAC_CHN1
-#error "DAC CHN1 not present in the selected device"
+#if STM32_DAC_USE_DAC1_CH1 && !STM32_HAS_DAC1_CH1
+#error "DAC1 CH1 not present in the selected device"
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && !STM32_HAS_DAC1_CH2
+#error "DAC1 CH2 not present in the selected device"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 && !STM32_HAS_DAC2_CH1
+#error "DAC2 CH1 not present in the selected device"
#endif
-#if STM32_DAC_USE_CHN2 && !STM32_HAS_DAC_CHN2
-#error "DAC CHN2 not present in the selected device"
+#if STM32_DAC_USE_DAC2_CH2 && !STM32_HAS_DAC2_CH2
+#error "DAC2 CH2 not present in the selected device"
#endif
-#if STM32_DAC_USE_CHN3 && !STM32_HAS_DAC_CHN3
-#error "DAC CHN3 not present in the selected device"
+#if (STM32_DAC_USE_DAC1_CH2 || STM32_DAC_USE_DAC2_CH2) && STM32_DAC_DUAL_MODE
+#error "DACx CH2 cannot be used independently in dual mode"
#endif
-#if !STM32_DAC_USE_CHN1 && !STM32_DAC_USE_CHN2 && !STM32_DAC_USE_CHN3
+#if !STM32_DAC_USE_DAC1_CH1 && !STM32_DAC_USE_DAC1_CH2 && \
+ !STM32_DAC_USE_DAC2_CH1 && !STM32_DAC_USE_DAC2_CH2
#error "DAC driver activated but no DAC peripheral assigned"
#endif
@@ -202,32 +174,41 @@ reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
-#if STM32_DAC_USE_CHN1 && !defined(STM32_DAC_CHN1_DMA_STREAM)
-#error "DAC1 CHN1 DMA stream not defined"
+#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC1_CH1_DMA_STREAM)
+#error "DAC1 CH1 DMA stream not defined"
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC1_CH2_DMA_STREAM)
+#error "DAC1 CH2 DMA stream not defined"
#endif
-#if STM32_DAC_USE_CHN2 && !defined(STM32_DAC_CHN2_DMA_STREAM)
-#error "DAC1 CHN2 DMA stream not defined"
+#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC2_CH1_DMA_STREAM)
+#error "DAC2 CH1 DMA stream not defined"
#endif
-#if STM32_DAC_USE_CHN3 && !defined(STM32_DAC_CHN3_DMA_STREAM)
-#error "DAC1 CHN3 DMA stream not defined"
+#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC2_CH2_DMA_STREAM)
+#error "DAC2 CH2 DMA stream not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
-#if STM32_DAC_USE_CHN1 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN1_DMA_STREAM, STM32_DAC_CHN1_DMA_MSK)
-#error "invalid DMA stream associated to DAC CHN1"
+#if STM32_DAC_USE_DAC1_CH1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
+#error "invalid DMA stream associated to DAC1 CH1"
#endif
-#if STM32_DAC_USE_CHN2 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN2_DMA_STREAM, STM32_DAC_CHN2_DMA_MSK)
-#error "invalid DMA stream associated to DAC CHN2"
+#if STM32_DAC_USE_DAC1_CH2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
+#error "invalid DMA stream associated to DAC1 CH2"
#endif
-#if STM32_DAC_USE_CHN3 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN3_DMA_STREAM, STM32_DAC_CHN3_DMA_MSK)
-#error "invalid DMA stream associated to DAC CHN3"
+#if STM32_DAC_USE_DAC2_CH1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
+#error "invalid DMA stream associated to DAC2 CH1"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
+#error "invalid DMA stream associated to DAC2 CH2"
#endif
#endif /* STM32_ADVANCED_DMA */
@@ -250,18 +231,44 @@ typedef struct DACDriver DACDriver; typedef uint16_t dacsample_t;
/**
+ * @brief Possible DAC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ DAC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ DAC_ERR_UNDERFLOW = 1 /**< DAC overflow condition. */
+} dacerror_t;
+
+/**
* @brief DAC notification callback type.
*
* @param[in] dacp pointer to the @p DACDriver object triggering the
+ * @param[in] buffer pointer to the next semi-buffer to be filled
+ * @param[in] n number of buffer rows available starting from @p buffer
* callback
*/
-typedef void (*daccallback_t)(DACDriver *dacp);
+typedef void (*daccallback_t)(DACDriver *dacp,
+ const dacsample_t *buffer,
+ size_t n);
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] dacp pointer to the @p DACDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*dacerrorcallback_t)(DACDriver *adcp, dacerror_t err);
+
+/**
+ * @brief Samples alignment and size mode.
+ */
typedef enum {
DAC_DHRM_12BIT_RIGHT = 0,
DAC_DHRM_12BIT_LEFT = 1,
DAC_DHRM_8BIT_RIGHT = 2,
-#if STM32_HAS_DAC_CHN2 && !defined(__DOXYGEN__)
+#if STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
DAC_DHRM_12BIT_RIGHT_DUAL = 3,
DAC_DHRM_12BIT_LEFT_DUAL = 4,
DAC_DHRM_8BIT_RIGHT_DUAL = 5
@@ -273,18 +280,18 @@ typedef enum { */
typedef struct {
/**
- * @brief Number of DAC channels.
+ * @brief Number of DAC channels.
*/
uint32_t num_channels;
/**
- * @brief Operation complete callback or @p NULL.
+ * @brief Operation complete callback or @p NULL.
*/
daccallback_t end_cb;
/**
- * @brief Error handling callback or @p NULL.
+ * @brief Error handling callback or @p NULL.
*/
- daccallback_t error_cb;
-
+ dacerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
} DACConversionGroup;
/**
@@ -292,18 +299,21 @@ typedef struct { */
typedef struct {
/**
- * @brief Timer frequency in Hz.
+ * @brief Initial sample to be presented on outputs.
*/
- uint32_t frequency;
+ dacsample_t sample;
/* End of the mandatory fields.*/
/**
* @brief DAC data holding register mode.
*/
dacdhrmode_t dhrm;
/**
- * @brief DAC initialization data.
+ * @brief DAC initialization data.
+ * @note This field contains the (not shifted) value to be put into the
+ * TSEL field of the DAC CR register during initialization. All
+ * other fields are handled internally.
*/
- uint32_t cr_flags;
+ uint32_t cr_tsel;
} DACConfig;
/**
@@ -311,34 +321,34 @@ typedef struct { */
struct DACDriver {
/**
- * @brief Driver state.
+ * @brief Driver state.
*/
dacstate_t state;
/**
- * @brief Conversion group.
+ * @brief Conversion group.
*/
const DACConversionGroup *grpp;
/**
- * @brief Samples buffer pointer.
+ * @brief Samples buffer pointer.
*/
const dacsample_t *samples;
/**
- * @brief Samples buffer size.
+ * @brief Samples buffer size.
*/
uint16_t depth;
/**
- * @brief Current configuration data.
+ * @brief Current configuration data.
*/
const DACConfig *config;
#if DAC_USE_WAIT || defined(__DOXYGEN__)
/**
- * @brief Waiting thread.
+ * @brief Waiting thread.
*/
thread_reference_t thread;
#endif /* DAC_USE_WAIT */
#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
/**
- * @brief Mutex protecting the bus.
+ * @brief Mutex protecting the bus.
*/
mutex_t mutex;
#endif /* DAC_USE_MUTUAL_EXCLUSION */
@@ -347,29 +357,17 @@ struct DACDriver { #endif
/* End of the mandatory fields.*/
/**
- * @brief Pointer to the DAC registers block.
+ * @brief Pointer to the DAC registers block.
*/
DAC_TypeDef *dac;
/**
- * @brief Pointer to the TIMx registers block.
- */
- stm32_tim_t *tim;
- /**
- * @brief The Timer IRQ priority.
- */
- uint32_t irqprio;
- /**
- * @brief Transmit DMA stream.
+ * @brief Transmit DMA stream.
*/
const stm32_dma_stream_t *dma;
/**
- * @brief TX DMA mode bit mask.
+ * @brief TX DMA mode bit mask.
*/
uint32_t dmamode;
- /**
- * @brief Timer base clock.
- */
- uint32_t clock;
};
/*===========================================================================*/
@@ -380,18 +378,22 @@ struct DACDriver { /* External declarations. */
/*===========================================================================*/
-#if STM32_DAC_USE_CHN1 && !defined(__DOXYGEN__)
+#if STM32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__)
extern DACDriver DACD1;
#endif
-#if STM32_DAC_USE_CHN2 && !defined(__DOXYGEN__)
+#if STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
extern DACDriver DACD2;
#endif
-#if STM32_DAC_USE_CHN3 && !defined(__DOXYGEN__)
+#if STM32_DAC_USE_DAC2_CH1 && !defined(__DOXYGEN__)
extern DACDriver DACD3;
#endif
+#if STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
+extern DACDriver DACD4;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
|