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-rw-r--r--os/hal/platforms/STM32F1xx/hal_lld.c3
-rw-r--r--os/hal/platforms/STM32F2xx/hal_lld.c3
-rw-r--r--os/hal/platforms/STM32F4xx/hal_lld.c3
-rw-r--r--os/hal/platforms/STM32L1xx/hal_lld.c3
4 files changed, 8 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c
index bc2b8b0f2..53bafb1b5 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.c
+++ b/os/hal/platforms/STM32F1xx/hal_lld.c
@@ -105,7 +105,8 @@ void hal_lld_init(void) {
SysTick_CTRL_TICKINT_Msk;
/* DWT cycle counter enable.*/
- DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+ SCS_DEMCR |= SCS_DEMCR_TRCENA;
+ DWT_CTRL |= DWT_CTRL_CYCCNTENA;
/* PWR and BD clocks enabled.*/
rccEnablePWRInterface(FALSE);
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c
index 1caa61d89..75d217c69 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.c
+++ b/os/hal/platforms/STM32F2xx/hal_lld.c
@@ -107,7 +107,8 @@ void hal_lld_init(void) {
SysTick_CTRL_TICKINT_Msk;
/* DWT cycle counter enable.*/
- DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+ SCS_DEMCR |= SCS_DEMCR_TRCENA;
+ DWT_CTRL |= DWT_CTRL_CYCCNTENA;
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index e7c09cc06..44de90602 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -107,7 +107,8 @@ void hal_lld_init(void) {
SysTick_CTRL_TICKINT_Msk;
/* DWT cycle counter enable.*/
- DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+ SCS_DEMCR |= SCS_DEMCR_TRCENA;
+ DWT_CTRL |= DWT_CTRL_CYCCNTENA;
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c
index df666815b..1d28df62b 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.c
+++ b/os/hal/platforms/STM32L1xx/hal_lld.c
@@ -104,7 +104,8 @@ void hal_lld_init(void) {
SysTick_CTRL_TICKINT_Msk;
/* DWT cycle counter enable.*/
- DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+ SCS_DEMCR |= SCS_DEMCR_TRCENA;
+ DWT_CTRL |= DWT_CTRL_CYCCNTENA;
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);