diff options
Diffstat (limited to 'os/hal/platforms/STM8')
| -rw-r--r-- | os/hal/platforms/STM8/hal_lld.c | 54 | ||||
| -rw-r--r-- | os/hal/platforms/STM8/hal_lld.h | 95 |
2 files changed, 119 insertions, 30 deletions
diff --git a/os/hal/platforms/STM8/hal_lld.c b/os/hal/platforms/STM8/hal_lld.c index 0cb3f5e25..de685aa30 100644 --- a/os/hal/platforms/STM8/hal_lld.c +++ b/os/hal/platforms/STM8/hal_lld.c @@ -50,36 +50,47 @@ /**
* @brief Low level HAL driver initialization.
+ * @details Clock sources initialization, HSI is assumed to be already
+ * started after reset.
+ * @note If the @p STM8_CLOCK_INIT option is set to @p FALSE then the
+ * initialization is not performed and is left to the application.
*
* @notapi
*/
void hal_lld_init(void) {
-#if STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT
-#if STM8_CLOCK_SOURCE == CLK_SOURCE_HSI
- CLK->ICKR = 1; /* HSIEN */
- while ((CLK->ICKR & 2) == 0) /* HSIRDY */
+#if !STM8_NO_CLOCK_INIT
+ /* Makes sure that HSI is stable before proceeding.*/
+ CLK->ICKR |= CLK_ICKR_HSIRDY;
+ while ((CLK->ICKR & CLK_ICKR_HSIRDY) == 0)
;
-#elif STM8_CLOCK_SOURCE == CLK_SOURCE_LSI
- CLK->ICKR = 8; /* LSIEN */
- while ((CLK->ICKR & 16) == 0) /* LSIRDY */
- ;
-#else /* STM8_CLOCK_SOURCE == CLK_SOURCE_HSE */
- CLK->ECKR = 1; /* HSEEN */
- while ((CLK->ECKR & 2) == 0) /* HSERDY */
+
+ /* LSI startup and stabilization if required.*/
+#if STM8_LSI_ENABLED
+ CLK->ICKR |= CLK_ICKR_LSIEN;
+ while ((CLK->ICKR & CLK_ICKR_LSIRDY) == 0)
;
#endif
-#if STM8_CLOCK_SOURCE != CLK_SOURCE_HSI
- /* Switching clock (manual switch mode).*/
- CLK->SWCR = 0;
- CLK->SWR = STM8_CLOCK_SOURCE;
- while ((CLK->SWCR & 8) == 0) /* SWIF */
+
+ /* HSE startup and stabilization if required.*/
+#if STM8_HSE_ENABLED
+ CLK->ECKR |= CLK_ECKCR_HSEEN;
+ while ((CLK->ECKR & CLK_ECKR_HSERDY) == 0)
;
- CLK->SWCR = 2; /* SWEN */
#endif
+
/* Setting up clock dividers.*/
CLK->CKDIVR = (STM8_HSI_DIVIDER << 3) | (STM8_CPU_DIVIDER << 0);
+ /* SYSCLK switch to the selected source, not necessary if it is HSI.*/
+#if STM8_SYSCLK_SOURCE != CLK_SYSSEL_HSI
+ /* Switching clock (manual switch mode).*/
+ CLK->SWR = STM8_SYSCLK_SOURCE;
+ while ((CLK->SWCR & CLK_SWCR_SWIF) == 0)
+ ;
+ CLK->SWCR = CLK_SWCR_SWEN;
+#endif
+
/* Clocks initially all disabled.*/
CLK->PCKENR1 = 0;
CLK->PCKENR2 = 0;
@@ -87,8 +98,13 @@ void hal_lld_init(void) { /* Other clock related initializations.*/
CLK->CSSR = 0;
CLK->CCOR = 0;
- CLK->CANCCR = 0;
-#endif /* STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT */
+ CLK->CANCCR = STM8_CAN_DIVIDER_VALUE;
+
+ /* HSI disabled if it is no more required.*/
+#if !STM8_HSI_ENABLED
+ CLK->ICKR &= ~CLK_ICKR_HSION;
+#endif
+#endif /* !STM8_NO_CLOCK_INIT */
}
/** @} */
diff --git a/os/hal/platforms/STM8/hal_lld.h b/os/hal/platforms/STM8/hal_lld.h index a7bcbe89a..6e2c585d2 100644 --- a/os/hal/platforms/STM8/hal_lld.h +++ b/os/hal/platforms/STM8/hal_lld.h @@ -20,6 +20,17 @@ /**
* @file STM8/hal_lld.h
* @brief STM8 HAL subsystem low level driver source.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - HSECLK (@p 0 if disabled or frequency in Hertz).
+ * .
+ * One of the following macros must also be defined:
+ * - STM8S103.
+ * - STM8S105.
+ * - STM8S207.
+ * - STM8S208.
+ * - STM8S903.
+ * .
*
* @addtogroup HAL
* @{
@@ -37,15 +48,14 @@ /**
* @brief Platform name.
*/
-#define PLATFORM_NAME "STM8x"
+#define PLATFORM_NAME "STM8S"
#define LSICLK 128000 /**< Low speed internal clock. */
#define HSICLK 16000000 /**< High speed internal clock. */
-#define CLK_SOURCE_DEFAULT 0 /**< No clock initialization. */
-#define CLK_SOURCE_HSI 0xE1 /**< HSI clock selector. */
-#define CLK_SOURCE_LSI 0xD2 /**< LSI clock selector. */
-#define CLK_SOURCE_HSE 0xB4 /**< HSE clock selector. */
+#define CLK_SYSSEL_HSI 0xE1 /**< HSI clock selector. */
+#define CLK_SYSSEL_LSI 0xD2 /**< LSI clock selector. */
+#define CLK_SYSSEL_HSE 0xB4 /**< HSE clock selector. */
#define CLK_HSI_DIV1 0 /**< HSI clock divided by 1. */
#define CLK_HSI_DIV2 1 /**< HSI clock divided by 2. */
@@ -66,10 +76,38 @@ /*===========================================================================*/
/**
+ * @brief Disables the clock initialization in the HAL.
+ */
+#if !defined(STM8_NO_CLOCK_INIT) || defined(__DOXYGEN__)
+#define STM8_NO_CLOCK_INIT FALSE
+#endif
+
+/**
+ * @brief Enables or disables the HSI clock source.
+ */
+#if !defined(STM8_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM8_HSI_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM8_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM8_LSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM8_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM8_HSE_ENABLED TRUE
+#endif
+
+/**
* @brief Clock source setting.
*/
-#if !defined(STM8_CLOCK_SOURCE) || defined(__DOXYGEN__)
-#define STM8_CLOCK_SOURCE CLK_SOURCE_DEFAULT
+#if !defined(STM8_SYSCLK_SOURCE) || defined(__DOXYGEN__)
+#define STM8_SYSCLK_SOURCE CLK_SYSSEL_HSE
#endif
/**
@@ -86,6 +124,13 @@ #define STM8_CPU_DIVIDER CLK_CPU_DIV1
#endif
+/**
+ * @brief bxCAN divider value.
+ */
+#if !defined(STM8_CAN_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define STM8_CAN_DIVIDER_VALUE 1
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -108,18 +153,46 @@ #error "specified invalid CPU divider"
#endif
-#if STM8_CLOCK_SOURCE == CLK_SOURCE_DEFAULT
+#if (STM8_CAN_DIVIDER_VALUE < 1) || (STM8_CAN_DIVIDER_VALUE > 8)
+#error "specified invalid CAN divider value"
+#endif
+
+#if STM8_HSE_ENABLED && (HSECLK == 0)
+#error "impossible to activate HSE"
+#endif
+
+#if !STM8_HSI_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSI)
+#error "requested HSI clock is not enabled"
+#endif
+
+#if !STM8_LSI_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_LSI)
+#error "requested LSI clock is not enabled"
+#endif
+
+#if !STM8_HSE_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSE)
+#error "requested HSE clock is not enabled"
+#endif
+
+/**
+ * @brief System clock.
+ */
+#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
#define SYSCLK (HSICLK / 8)
-#elif STM8_CLOCK_SOURCE == CLK_SOURCE_HSI
+#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSI
#define SYSCLK (HSICLK / (1 << STM8_HSI_DIVIDER))
-#elif STM8_CLOCK_SOURCE == CLK_SOURCE_LSI
+#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_LSI
#define SYSCLK LSICLK
-#elif STM8_CLOCK_SOURCE == CLK_SOURCE_HSE
+#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSE
#define SYSCLK HSECLK
#else
#error "specified invalid clock source"
#endif
+/**
+ * @brief CPU clock.
+ * @details On the STM8S the CPU clock can be programmed to be a fraction of
+ * the system clock. + */
#define CPUCLK (SYSCLK / (1 << STM8_CPU_DIVIDER))
/*===========================================================================*/
|