diff options
Diffstat (limited to 'os/hal/platforms/STM32F1xx/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld.c | 67 |
1 files changed, 48 insertions, 19 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c index 653201363..bf3baca8a 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.c +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -41,6 +41,47 @@ /* Driver local functions. */
/*===========================================================================*/
+/**
+ * @brief Initializes the backup domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Backup domain access enabled during initialization.*/
+ PWR->CR |= PWR_CR_DBP;
+
+ /* RTC clock initialization.*/
+#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+ /* RTC clock not required, backup domain reset as initialization.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+ /* Backup domain reset.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ RCC->BDCR |= RCC_BDCR_LSEON;
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+ /* Selects clock source.*/
+ RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
+
+ /* RTC enabled regardless its previous status, this will also prevent
+ successive initializations.*/
+ RCC->BDCR |= RCC_BDCR_RTCEN;
+ }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+
+ /* Backup domain access disabled for operations safety.*/
+ PWR->CR &= ~PWR_CR_DBP;
+}
+
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@@ -70,13 +111,19 @@ void hal_lld_init(void) { /* DWT cycle counter enable.*/
DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+ /* PWR and BD clocks enabled.*/
+ rccEnablePWRInterface(FALSE);
+ rccEnableBKPInterface(FALSE);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
- rccEnablePWRInterface(FALSE);
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
}
@@ -122,15 +169,6 @@ void stm32_clock_init(void) { ; /* Waits until LSI is stable. */
#endif
-#if STM32_LSE_ENABLED
- /* LSE activation, have to unlock the register.*/
- PWR->CR |= PWR_CR_DBP;
- RCC->BDCR |= RCC_BDCR_LSEON;
- while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
- ; /* Waits until LSE is stable. */
- PWR->CR &= ~PWR_CR_DBP;
-#endif
-
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
@@ -193,15 +231,6 @@ void stm32_clock_init(void) { ; /* Waits until LSI is stable. */
#endif
-#if STM32_LSE_ENABLED
- /* LSE activation, have to unlock the register.*/
- PWR->CR |= PWR_CR_DBP;
- RCC->BDCR |= RCC_BDCR_LSEON;
- while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
- ; /* Waits until LSE is stable. */
- PWR->CR &= ~PWR_CR_DBP;
-#endif
-
/* Settings of various dividers and multipliers in CFGR2.*/
RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
STM32_PREDIV1 | STM32_PREDIV1SRC;
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